conference paper · International Conference on Computer Aided Design · 2003

VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)

Cited by 13Abstract and details only

Abstract

A description is given of techniques for simulation modeling and of a physical design verification methodology for assuring simulation and interconnection correspondence. Following the introductory material, details of the simulation model are presented. Then a description of a physical design verification methodology is given, followed by results from current designs, and key points are summarized.>

Cite this paper

APA 7

Stanisic, B. R., & Brown, M. (2003). VHDL modeling for analog-digital hardware designs (VHSIS hardware description language). International Conference on Computer Aided Design, 184–187. https://doi.org/10.1109/iccad.1989.76932

MLA 9

Stanisic, Balsha R., and Mark Brown. “VHDL modeling for analog-digital hardware designs (VHSIS hardware description language).” International Conference on Computer Aided Design, 2003, pp. 184–87, https://doi.org/10.1109/iccad.1989.76932.

Chicago

Stanisic, Balsha R., and Mark Brown. 2003. “VHDL modeling for analog-digital hardware designs (VHSIS hardware description language).” International Conference on Computer Aided Design: 184–87. https://doi.org/10.1109/iccad.1989.76932.

Harvard

Stanisic, B.R. and Brown, M. (2003) ‘VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)’, International Conference on Computer Aided Design, pp. 184–187. Available at: https://doi.org/10.1109/iccad.1989.76932.

BibTeX

@article{stanisic2003vhdl,
  title = {{VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)}},
  author = {Stanisic, Balsha R. and Brown, Mark},
  journal = {International Conference on Computer Aided Design},
  pages = {184--187},
  year = {2003},
  doi = {10.1109/iccad.1989.76932}
}

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