A Fine-Grained Analysis of the Performance and Power Benefits of Compiler Optimizations for Embedded Devices.

Abstract

In this study we examine the performance and power benefits resulting from many traditional and aggressive compiler optimizations. Examples of early and loop optimizations were translated from classic compiler textbooks into PowerPC assembly and executed in the Dynamic Super-Scalar Wattch simulation environment. Each optimization was applied in an isolated manner which resulted in an overall average improvement in performance of 4.8 % and a 6.2 % decrease in power consumption for the early optimizations. The loop optimizations yielded greater performance and power improvements with an average speed-up of 17.0% and a 15.3 % reduction in power consumption. The decrease in power consumption of the early optimizations was found to correspond closely to the execution time. In contrast, the improvements from the loop optimizations were found to correspond to the number of instructions committed. The average decrease in the number of instructions committed was found to be 6.2 % and 14.1 % for the early and loop optimizations, respectively. The goal of this study is to provide guidance to compiler writers when developing methods to select optimizations if power consumption is of importance. 1.

Cite this paper

@article{selby2006fine,
  title = {{A Fine-Grained Analysis of the Performance and Power Benefits of Compiler Optimizations for Embedded Devices.}},
  author = {Selby, Jason W. A. and Giesbrecht, Mark W.},
  pages = {821--827},
  year = {2006}
}

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