conference paper · IEEE International Conference on Progress in Informatics and Computing · 2014

Accelerating embarrassingly parallel algorithm on Intel MIC

Qinglin Wang, Jie Liu, Xiantuo Tang, Feng Wang, Guitao Fu, Zuocheng Xing

Cited by 17Abstract and details only

Abstract

The Embarrassingly Parallel (EP) algorithm which is typical of many Monte Carlo applications provides an estimate of the upper achievable limits for double precision performance of parallel supercomputers. Recently, Intel released Many Integrated Core (MIC) architecture as a many-core co-processor. MIC often offers more than 50 cores each of which can run four hardware threads as well as 512-bit vector instructions. In this paper, we describe how the EP algorithm is accelerated effectively on the platforms containing MIC using the offload execution model. The result shows that the efficient implementation of EP algorithm on MIC can take full advantage of MIC's computational resources and achieves a speedup of 3.06 compared with that on Intel Xeon E5-2670 CPU. Based on the EP algorithm on MIC and an effective task distribution model, the implementation of EP algorithm on a CPU-MIC heterogeneous platform achieves the performance of up to 2134.86 Mop/s and 4.04 times speedup compared with that on Intel Xeon E5-2670 CPU.

Cite this paper

APA 7

Wang, Q., Liu, J., Tang, X., Wang, F., Fu, G., & Xing, Z. (2014). Accelerating embarrassingly parallel algorithm on Intel MIC. IEEE International Conference on Progress in Informatics and Computing, 213–218. https://doi.org/10.1109/pic.2014.6972327

MLA 9

Wang, Qinglin, et al. “Accelerating embarrassingly parallel algorithm on Intel MIC.” IEEE International Conference on Progress in Informatics and Computing, 2014, pp. 213–18, https://doi.org/10.1109/pic.2014.6972327.

Chicago

Wang, Qinglin, Jie Liu, Xiantuo Tang, Feng Wang, Guitao Fu, and Zuocheng Xing. 2014. “Accelerating embarrassingly parallel algorithm on Intel MIC.” IEEE International Conference on Progress in Informatics and Computing: 213–18. https://doi.org/10.1109/pic.2014.6972327.

Harvard

Wang, Q. et al. (2014) ‘Accelerating embarrassingly parallel algorithm on Intel MIC’, IEEE International Conference on Progress in Informatics and Computing, pp. 213–218. Available at: https://doi.org/10.1109/pic.2014.6972327.

BibTeX

@article{wang2014accelerating,
  title = {{Accelerating embarrassingly parallel algorithm on Intel MIC}},
  author = {Wang, Qinglin and Liu, Jie and Tang, Xiantuo and Wang, Feng and Fu, Guitao and Xing, Zuocheng},
  journal = {IEEE International Conference on Progress in Informatics and Computing},
  pages = {213--218},
  year = {2014},
  doi = {10.1109/pic.2014.6972327}
}

Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.