article · 1997

An extended addressing mode for low power

Cited by 25Abstract and details only

Abstract

This paper demonstrates the feasibility of a register-memory addressing mode in microprocessors targeted for low power applications. Using a high level power profiling tool that performs software energy evaluation, the major sources of power dissipation in a typical RISC processor are identified. It is shown that the addition of a register-memory addressing mode can target these hot-spots and provide power savings. Two different implementation options are considered and the power-performance trade-offs are evaluated. The reduction in performance is cushioned by the reduced instruction count and it is anticipated that the overall impact on the total execution time of programs will be acceptable in low power application domains.

Cite this paper

APA 7

Kalambur, A., & Irwin, M. (1997). An extended addressing mode for low power. https://doi.org/10.1145/263272.263336

MLA 9

Kalambur, Atul, and M.J. Irwin. “An extended addressing mode for low power.” 1997, pp. 208–13, https://doi.org/10.1145/263272.263336.

Chicago

Kalambur, Atul, and M.J. Irwin. 1997. “An extended addressing mode for low power.” https://doi.org/10.1145/263272.263336.

Harvard

Kalambur, A. and Irwin, M. (1997) ‘An extended addressing mode for low power’. Available at: https://doi.org/10.1145/263272.263336.

BibTeX

@article{kalambur1997extended,
  title = {{An extended addressing mode for low power}},
  author = {Kalambur, Atul and Irwin, M.J.},
  pages = {208--213},
  year = {1997},
  doi = {10.1145/263272.263336}
}

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