article · 1992

Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture

Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita

Cited by 2Abstract and details only

Abstract

This paper presents the benchmark results on a vector-processor prototype based on the MSFV (multithreaded streaming/FIFO vector) architecture. The MSFV architecture is single-chip oriented, and thus its main object is to save the off-chip memory bandwidth by exploiting the register bandwidth instead. The register bandwidth is exploited by the synergism of FIFO register, chaining, streaming, and multithreading. This paper tries to identify the strength and weakness of those architectural features. The results for basic vector operations and Livermore Fortran Kernels are reported in terms of normalized FLOPC (floating-point operations per clock cycle) and compared to previously-reported results on the Cray X-MP, Y-MP, Fujitsu VP-200, Hitachi S-810/20, NEC SX-2, and SX-3. These comparisons show that, for many basic vector operations, the execution rate of the MSFV prototype results in worst due to its saving the memory bandwidth. However, for Livermore Fortran Kernels, the MSFV prototype results in worst due to its saving the memory bandwidth. However, for Livermore Fortran Kernels, the MSFV prototype outperforms the VP-200 by 2.11 times (geometric mean) and one processor of the X-MP by 1.22 times (geometric mean) in terms of FLOPC. Also, it is 0.67 times (geometric mean) faster than the S-810/20, and 0.76 times (geometric mean) faster than the SX-2. The paper concludes that the MSFV architecture is successful in saving the memory bandwidth.

Cite this paper

APA 7

Hironaka, T., Hashimoto, T., Okazaki, K., Murakami, K., & Tomita, S. (1992). Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. https://doi.org/10.1145/143369.143420

MLA 9

Hironaka, Tetsuo, et al. “Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.” 1992, pp. 272–81, https://doi.org/10.1145/143369.143420.

Chicago

Hironaka, Tetsuo, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, and Shinji Tomita. 1992. “Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.” https://doi.org/10.1145/143369.143420.

Harvard

Hironaka, T. et al. (1992) ‘Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture’. Available at: https://doi.org/10.1145/143369.143420.

BibTeX

@article{hironaka1992benchmarking,
  title = {{Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture}},
  author = {Hironaka, Tetsuo and Hashimoto, Takashi and Okazaki, Keizo and Murakami, Kazuaki and Tomita, Shinji},
  pages = {272--281},
  year = {1992},
  doi = {10.1145/143369.143420}
}

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