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article · International Journal of Pattern Recognition and Artificial Intelligence · 1995

A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS

N. VENKATESWARAN, Srividhya Pattabiraman, Jayant DeSouza, G. Sriram, Ramachandran Srinivasan, R. SANKAR, G. SURESH

Cited by 1Abstract and details only

Abstract

The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable Pacube (PA3—Programmable Array of Array Adders) VLSI array is proposed in this paper. These arrays can be mask programmed for building cost-effective super computing VLSI functional units. Another important feature is the architecture of the macro-cell, which is designed in such a way that the functional units corresponding to the G-set equations when mapped on the macro-cell arrays possess identical data flow control. This leads to a highly simplified control design for executing complex computations.

Cite this paper

APA 7

VENKATESWARAN, N., Pattabiraman, S., DeSouza, J., Sriram, G., Srinivasan, R., SANKAR, R., & SURESH, G. (1995). A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS. International Journal of Pattern Recognition and Artificial Intelligence, 09(02), 263–301. https://doi.org/10.1142/s0218001495000134

MLA 9

VENKATESWARAN, N., et al. “A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS.” International Journal of Pattern Recognition and Artificial Intelligence, vol. 09, no. 02, 1995, pp. 263–301, https://doi.org/10.1142/s0218001495000134.

Chicago

VENKATESWARAN, N., Srividhya Pattabiraman, Jayant DeSouza, G. Sriram, Ramachandran Srinivasan, R. SANKAR, and G. SURESH. 1995. “A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS.” International Journal of Pattern Recognition and Artificial Intelligence 09 (02): 263–301. https://doi.org/10.1142/s0218001495000134.

Harvard

VENKATESWARAN, N. et al. (1995) ‘A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS’, International Journal of Pattern Recognition and Artificial Intelligence, 09(02), pp. 263–301. Available at: https://doi.org/10.1142/s0218001495000134.

BibTeX
@article{venkateswaran1995design,
  title = {{A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS}},
  author = {VENKATESWARAN, N. and Pattabiraman, Srividhya and DeSouza, Jayant and Sriram, G. and Srinivasan, Ramachandran and SANKAR, R. and SURESH, G.},
  journal = {International Journal of Pattern Recognition and Artificial Intelligence},
  volume = {09},
  number = {02},
  pages = {263--301},
  year = {1995},
  doi = {10.1142/s0218001495000134}
}

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