article · 2006
Optimal TDMA time slot and cycle length allocation for hard real-time systems
Ernesto Wandeler, Lothar Thiele
Cited by 66Abstract and details only
Abstract
We present an analytic method to determine the provably smallest possible slot length that must be allocated in a TDMA resource, to serve an event-triggered hard real-time load with arbitrary deterministic timing behavior. Based on this method, we then present constructive methods to find all feasible as well as the optimal cycle length in a TDMA resource, and we show how to determine the minimum required band-width of a TDMA resource. We demonstrate the applicability and computational efficiency of the presented methods in a case study of a large distributed embedded system with a TDMA bus, where we will find the optimal parameter set for the TDMA bus.
Cite this paper
Wandeler, E., & Thiele, L. (2006). Optimal TDMA time slot and cycle length allocation for hard real-time systems. https://doi.org/10.1145/1118299.1118417
Wandeler, Ernesto, and Lothar Thiele. “Optimal TDMA time slot and cycle length allocation for hard real-time systems.” 2006, p. 479, https://doi.org/10.1145/1118299.1118417.
Wandeler, Ernesto, and Lothar Thiele. 2006. “Optimal TDMA time slot and cycle length allocation for hard real-time systems.” https://doi.org/10.1145/1118299.1118417.
Wandeler, E. and Thiele, L. (2006) ‘Optimal TDMA time slot and cycle length allocation for hard real-time systems’. Available at: https://doi.org/10.1145/1118299.1118417.
@article{wandeler2006optimal,
title = {{Optimal TDMA time slot and cycle length allocation for hard real-time systems}},
author = {Wandeler, Ernesto and Thiele, Lothar},
pages = {479},
year = {2006},
doi = {10.1145/1118299.1118417}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.