article · Electronics Letters · 2008

Fast CABAC decoding architecture

Cited by 13Abstract and details only

Abstract

A novel high-performance decoding architecture for H.264 context-based adaptive binary arithmetic coding (CABAC) is presented, where several efficient techniques such as speculative decoding, table-based calculation, logic balancing, mathematic reordering and optimal retiming are adopted to reduce the critical timing path. Simulation and implementation results show that the architecture can achieve a fixed decoding rate of up to 247.5 Mbin/s, which is 67% faster than conventional architectures.

Cite this paper

APA 7

Zhang, P. (2008). Fast CABAC decoding architecture. Electronics Letters, 44(24), 1394–1396. https://doi.org/10.1049/el:20082126

MLA 9

Zhang, P. “Fast CABAC decoding architecture.” Electronics Letters, vol. 44, no. 24, 2008, pp. 1394–96, https://doi.org/10.1049/el:20082126.

Chicago

Zhang, P. 2008. “Fast CABAC decoding architecture.” Electronics Letters 44 (24): 1394–96. https://doi.org/10.1049/el:20082126.

Harvard

Zhang, P. (2008) ‘Fast CABAC decoding architecture’, Electronics Letters, 44(24), pp. 1394–1396. Available at: https://doi.org/10.1049/el:20082126.

BibTeX

@article{zhang2008fast,
  title = {{Fast CABAC decoding architecture}},
  author = {Zhang, P.},
  journal = {Electronics Letters},
  volume = {44},
  number = {24},
  pages = {1394--1396},
  year = {2008},
  doi = {10.1049/el:20082126}
}

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