article · Journal of Parallel and Distributed Computing · 1997

A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip

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Abstract

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Cite this paper

Murtagh, P. J., & Tsoi, A. C. (1997). A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip. Journal of Parallel and Distributed Computing, 44(1), 53–70. https://doi.org/10.1006/jpdc.1997.1343

MLA 9

Murtagh, P. J., and Ah Chung Tsoi. “A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip.” Journal of Parallel and Distributed Computing, vol. 44, no. 1, 1997, pp. 53–70, https://doi.org/10.1006/jpdc.1997.1343.

Chicago

Murtagh, P. J., and Ah Chung Tsoi. 1997. “A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip.” Journal of Parallel and Distributed Computing 44 (1): 53–70. https://doi.org/10.1006/jpdc.1997.1343.

Harvard

Murtagh, P.J. and Tsoi, A.C. (1997) ‘A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip’, Journal of Parallel and Distributed Computing, 44(1), pp. 53–70. Available at: https://doi.org/10.1006/jpdc.1997.1343.

BibTeX

@article{murtagh1997reconfigurable,
  title = {{A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip}},
  author = {Murtagh, P. J. and Tsoi, Ah Chung},
  journal = {Journal of Parallel and Distributed Computing},
  volume = {44},
  number = {1},
  pages = {53--70},
  year = {1997},
  doi = {10.1006/jpdc.1997.1343}
}

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