article · 2002

Analysis and improvement of high-speed SDH frame alignment

Yanping Sha, Wang Hansheng, Lieguang Zeng

Cited by 0Abstract and details only

Abstract

The frame aligner is a key part in a digital multiplexer/demultiplexer system. A novel error tolerant frame alignment methodology is presented in this paper. Analysis shows that this method complies with ITU-T recommendation and improves the performance. The parameters of frame aligner and framing pattern are carefully selected. Finally, the parallel realization of a frame aligner with the proposed method, which can lower the working frequency and power, is applied in an STM-4 system.

Cite this paper

APA 7

Sha, Y., Hansheng, W., & Zeng, L. (2002). Analysis and improvement of high-speed SDH frame alignment. https://doi.org/10.1109/icct.2000.890850

MLA 9

Sha, Yanping, et al. “Analysis and improvement of high-speed SDH frame alignment.” vol. 2, 2002, pp. 1024–27, https://doi.org/10.1109/icct.2000.890850.

Chicago

Sha, Yanping, Wang Hansheng, and Lieguang Zeng. 2002. “Analysis and improvement of high-speed SDH frame alignment.” https://doi.org/10.1109/icct.2000.890850.

Harvard

Sha, Y., Hansheng, W. and Zeng, L. (2002) ‘Analysis and improvement of high-speed SDH frame alignment’. Available at: https://doi.org/10.1109/icct.2000.890850.

BibTeX

@article{sha2002analysis,
  title = {{Analysis and improvement of high-speed SDH frame alignment}},
  author = {Sha, Yanping and Hansheng, Wang and Zeng, Lieguang},
  volume = {2},
  pages = {1024--1027},
  year = {2002},
  doi = {10.1109/icct.2000.890850}
}

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