article · IEEE Transactions on Computers · 1990
Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
Cited by 219Abstract and details only
Abstract
The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts is presented. Simulation studies show that by resolving dependencies the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts.>
Cite this paper
Sohi, G. S. (1990). Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Transactions on Computers, 39(3), 349–359. https://doi.org/10.1109/12.48865
Sohi, Gurindar S. “Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers.” IEEE Transactions on Computers, vol. 39, no. 3, 1990, pp. 349–59, https://doi.org/10.1109/12.48865.
Sohi, Gurindar S. 1990. “Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers.” IEEE Transactions on Computers 39 (3): 349–59. https://doi.org/10.1109/12.48865.
Sohi, G.S. (1990) ‘Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers’, IEEE Transactions on Computers, 39(3), pp. 349–359. Available at: https://doi.org/10.1109/12.48865.
@article{sohi1990instruction,
title = {{Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers}},
author = {Sohi, Gurindar S.},
journal = {IEEE Transactions on Computers},
volume = {39},
number = {3},
pages = {349--359},
year = {1990},
doi = {10.1109/12.48865}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.