conference paper · ACM/IEEE Design Automation Conference (DAC) · 1987

A vector hardware accelerator with circuit simulation emphasis

Andrei Vladimirescu, Don Weiss, Manolis G. H. Katevenis, Zvika Bronstein, A. Kifir, K. Danuwidjaja, K. C. Ng., N. Jain, Stanley E. Lass

Cited by 6Abstract and details only

Abstract

A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650.

Cite this paper

APA 7

Vladimirescu, A., Weiss, D., Katevenis, M. G. H., Bronstein, Z., Kifir, A., Danuwidjaja, K., Ng., K. C., Jain, N., & Lass, S. E. (1987). A vector hardware accelerator with circuit simulation emphasis. ACM/IEEE Design Automation Conference (DAC), 89–94. https://doi.org/10.1145/37888.37901

MLA 9

Vladimirescu, Andrei, et al. “A vector hardware accelerator with circuit simulation emphasis.” ACM/IEEE Design Automation Conference (DAC), 1987, pp. 89–94, https://doi.org/10.1145/37888.37901.

Chicago

Vladimirescu, Andrei, Don Weiss, Manolis G. H. Katevenis, Zvika Bronstein, A. Kifir, K. Danuwidjaja, K. C. Ng., N. Jain, and Stanley E. Lass. 1987. “A vector hardware accelerator with circuit simulation emphasis.” ACM/IEEE Design Automation Conference (DAC): 89–94. https://doi.org/10.1145/37888.37901.

Harvard

Vladimirescu, A. et al. (1987) ‘A vector hardware accelerator with circuit simulation emphasis’, ACM/IEEE Design Automation Conference (DAC), pp. 89–94. Available at: https://doi.org/10.1145/37888.37901.

BibTeX

@article{vladimirescu1987vector,
  title = {{A vector hardware accelerator with circuit simulation emphasis}},
  author = {Vladimirescu, Andrei and Weiss, Don and Katevenis, Manolis G. H. and Bronstein, Zvika and Kifir, A. and Danuwidjaja, K. and Ng., K. C. and Jain, N. and Lass, Stanley E.},
  journal = {ACM/IEEE Design Automation Conference (DAC)},
  pages = {89--94},
  year = {1987},
  doi = {10.1145/37888.37901}
}

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