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article · IEEE Transactions on Computers · 2003

An intelligent cache system with hardware prefetching for high performance

Jung-Hoon Lee, Seh-Woong Jeong, Shin‐Dug Kim, Charles Weems

Cited by 14Abstract and details only

Abstract

We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. The proposed cache, which we call a selective-mode intelligent (SMI) cache, consists of three parts: a direct-mapped cache with a small block size, a fully associative spatial buffer with a large block size, and a hardware prefetching unit. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer for a time period. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. The overhead of this prefetching operation is shown to be negligible. We also show that the prefetch operation is highly accurate: Over 90 percent of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance. Also, the SMI cache can reduce the miss ratio by around 20 percent and the average memory access time by 10 percent, compared with a victim-buffer cache configuration.

Cite this paper

APA 7

Lee, J.-H., Jeong, S.-W., Kim, S., & Weems, C. (2003). An intelligent cache system with hardware prefetching for high performance. IEEE Transactions on Computers, 52(5), 607–616. https://doi.org/10.1109/tc.2003.1197127

MLA 9

Lee, Jung-Hoon, et al. “An intelligent cache system with hardware prefetching for high performance.” IEEE Transactions on Computers, vol. 52, no. 5, 2003, pp. 607–16, https://doi.org/10.1109/tc.2003.1197127.

Chicago

Lee, Jung-Hoon, Seh-Woong Jeong, Shin‐Dug Kim, and Charles Weems. 2003. “An intelligent cache system with hardware prefetching for high performance.” IEEE Transactions on Computers 52 (5): 607–16. https://doi.org/10.1109/tc.2003.1197127.

Harvard

Lee, J.-H. et al. (2003) ‘An intelligent cache system with hardware prefetching for high performance’, IEEE Transactions on Computers, 52(5), pp. 607–616. Available at: https://doi.org/10.1109/tc.2003.1197127.

BibTeX
@article{lee2003intelligent,
  title = {{An intelligent cache system with hardware prefetching for high performance}},
  author = {Lee, Jung-Hoon and Jeong, Seh-Woong and Kim, Shin‐Dug and Weems, Charles},
  journal = {IEEE Transactions on Computers},
  volume = {52},
  number = {5},
  pages = {607--616},
  year = {2003},
  doi = {10.1109/tc.2003.1197127}
}

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