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article · IEEE Spectrum · 1995

Multithreaded processor architectures

Gregory T. Byrd, Mark A. Holliday

Cited by 39Abstract and details only

Abstract

The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution. When a long-latency operation occurs in one of the threads, another begins execution. In this way, useful work is performed while the time-consuming operation is completed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cite this paper

APA 7

Byrd, G. T., & Holliday, M. A. (1995). Multithreaded processor architectures. IEEE Spectrum, 32(8), 38–46. https://doi.org/10.1109/6.402166

MLA 9

Byrd, Gregory T., and Mark A. Holliday. “Multithreaded processor architectures.” IEEE Spectrum, vol. 32, no. 8, 1995, pp. 38–46, https://doi.org/10.1109/6.402166.

Chicago

Byrd, Gregory T., and Mark A. Holliday. 1995. “Multithreaded processor architectures.” IEEE Spectrum 32 (8): 38–46. https://doi.org/10.1109/6.402166.

Harvard

Byrd, G.T. and Holliday, M.A. (1995) ‘Multithreaded processor architectures’, IEEE Spectrum, 32(8), pp. 38–46. Available at: https://doi.org/10.1109/6.402166.

BibTeX
@article{byrd1995multithreaded,
  title = {{Multithreaded processor architectures}},
  author = {Byrd, Gregory T. and Holliday, Mark A.},
  journal = {IEEE Spectrum},
  volume = {32},
  number = {8},
  pages = {38--46},
  year = {1995},
  doi = {10.1109/6.402166}
}

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