article · 2006
Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication
Guo Li, Wang Miao-feng, Tian Qiu, Lu Liu, Luo Feng
Cited by 1Abstract and details only
Abstract
Based on Horner' rule and Baugh-Wooley algorithm, this paper presents two novel bit-level parallel array algorithms of 2's complement multiplication, and the algorithms have been mapped to systolic arrays by using linear mapping techniques. We propose two efficient systolic arrays of multiply and accumulate (MAC) operation and we also describe the vector-vector and matrix-matrix multiplication that can be efficiently implemented by using the MAC arrays. The two systolic arrays have high performance (low time complexity, space complexity and latency) and consume smaller gate-area in comparison to other architectures. It is suitable for VLSI implementation for its regularity and modularity
Cite this paper
Li, G., Miao-feng, W., Qiu, T., Liu, L., & Feng, L. (2006). Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication. https://doi.org/10.1109/icccas.2006.284700
Li, Guo, et al. “Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication.” 2006, pp. 567–70, https://doi.org/10.1109/icccas.2006.284700.
Li, Guo, Wang Miao-feng, Tian Qiu, Lu Liu, and Luo Feng. 2006. “Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication.” https://doi.org/10.1109/icccas.2006.284700.
Li, G. et al. (2006) ‘Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication’. Available at: https://doi.org/10.1109/icccas.2006.284700.
@article{li2006level,
title = {{Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication}},
author = {Li, Guo and Miao-feng, Wang and Qiu, Tian and Liu, Lu and Feng, Luo},
pages = {567--570},
year = {2006},
doi = {10.1109/icccas.2006.284700}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.