article · 2002
Comparison of 32-bit multipliers for various performance measures
S.Y.A. Shah, A.J. Al-Khalili, D. Al-Khalili
Cited by 37Abstract and details only
Abstract
Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tree multiplier, combined modified Booth-Wallace tree multiplier and twin pipe serial parallel multiplier. Comparison is based on synthesis results obtained by synthesizing all multiplier architectures towards FPGA.
Cite this paper
Shah, S., Al-Khalili, A., & Al-Khalili, D. (2002). Comparison of 32-bit multipliers for various performance measures. https://doi.org/10.1109/icm.2000.916418
Shah, S.Y.A., et al. “Comparison of 32-bit multipliers for various performance measures.” 2002, pp. 75–80, https://doi.org/10.1109/icm.2000.916418.
Shah, S.Y.A., A.J. Al-Khalili, and D. Al-Khalili. 2002. “Comparison of 32-bit multipliers for various performance measures.” https://doi.org/10.1109/icm.2000.916418.
Shah, S., Al-Khalili, A. and Al-Khalili, D. (2002) ‘Comparison of 32-bit multipliers for various performance measures’. Available at: https://doi.org/10.1109/icm.2000.916418.
@article{shah2002comparison,
title = {{Comparison of 32-bit multipliers for various performance measures}},
author = {Shah, S.Y.A. and Al-Khalili, A.J. and Al-Khalili, D.},
pages = {75--80},
year = {2002},
doi = {10.1109/icm.2000.916418}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.