article · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999
Processor array design with FPGA area constraint
Cited by 1Abstract and details only
Abstract
Digital signal processing algorithms with multiple shift-invariant dependence graphs (DGs) can be mapped to field programmable gate array hardware in many different types of systolic processor arrays. Because of the finite amount of hardware resources, the problem is to use a "right" amount of hardware in a specific configuration so to maximize the processing speed. In this paper, the problem of finding the right processor array configuration is formulated as a constrained optimization problem where the cost function includes not only the cost of individual processor arrays but also the cost of interfacing circuits. Three heuristic algorithms are presented for the optimization problem. Among them, both the Lth axial neighbor algorithm and the simulated annealing algorithm produce good results on a test case. Simulation results on the test case also indicate that the initial configuration is important in getting a good configuration for both algorithms. The Lth axial neighbor algorithm has the extra advantage of requiring less amount of performance tuning.
Cite this paper
Fernando, J., & Jean, J. (1999). Processor array design with FPGA area constraint. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(3), 253–264. https://doi.org/10.1109/43.748156
Fernando, Joseph, and Jack Jean. “Processor array design with FPGA area constraint.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, 1999, pp. 253–64, https://doi.org/10.1109/43.748156.
Fernando, Joseph, and Jack Jean. 1999. “Processor array design with FPGA area constraint.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18 (3): 253–64. https://doi.org/10.1109/43.748156.
Fernando, J. and Jean, J. (1999) ‘Processor array design with FPGA area constraint’, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(3), pp. 253–264. Available at: https://doi.org/10.1109/43.748156.
@article{fernando1999processor,
title = {{Processor array design with FPGA area constraint}},
author = {Fernando, Joseph and Jean, Jack},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
volume = {18},
number = {3},
pages = {253--264},
year = {1999},
doi = {10.1109/43.748156}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.