article · 2012
A compact FPGA implementation of a bit-serial SIMD cellular processor array
Cited by 10Abstract and details only
Abstract
An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated.
Cite this paper
Walsh, D., & Dudek, P. (2012). A compact FPGA implementation of a bit-serial SIMD cellular processor array. https://doi.org/10.1109/cnna.2012.6331450
Walsh, Declan, and Piotr Dudek. “A compact FPGA implementation of a bit-serial SIMD cellular processor array.” 2012, pp. 1–6, https://doi.org/10.1109/cnna.2012.6331450.
Walsh, Declan, and Piotr Dudek. 2012. “A compact FPGA implementation of a bit-serial SIMD cellular processor array.” https://doi.org/10.1109/cnna.2012.6331450.
Walsh, D. and Dudek, P. (2012) ‘A compact FPGA implementation of a bit-serial SIMD cellular processor array’. Available at: https://doi.org/10.1109/cnna.2012.6331450.
@article{walsh2012compact,
title = {{A compact FPGA implementation of a bit-serial SIMD cellular processor array}},
author = {Walsh, Declan and Dudek, Piotr},
pages = {1--6},
year = {2012},
doi = {10.1109/cnna.2012.6331450}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.