Gate delay fault test generation for non-scan circuits

Abstract

This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation- backward justification technique: The test pattern generation is started at the fault location, and after successful "local " test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this paper. 1

Cite this paper

@article{vanbrakel1995gate,
  title = {{Gate delay fault test generation for non-scan circuits}},
  author = {van Brakel, G. and Gläser, U. and Kerkhoff, Hans G. and Vierhaus, H.T.},
  pages = {308--312},
  year = {1995},
  doi = {10.5555/787258.787453}
}

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