article · Journal of Computers · 2007

Partially Reconfigurable Vector Processor for Embedded Applications

Cited by 0Abstract and details only

Abstract

Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, automotive, networking, and consumer products. These systems require efficient devices that occupy small area and consume low power. The device area can be minimized by reusing the same hardware for different applications. If possible, reconfiguring the hardware to adapt to the application needs is important for reducing execution time and/or power consumption. Partial reconfiguration facilitates minimum hardware changes to form a new configuration. We have designed a reconfigurable vector processor for embedded applications. Benchmark results on Xilinx FPGAs (Field Programmable Gate Arrays) are presented involving partial reconfiguration for embedded applications that process vectors. Two approaches are studied toward performance evaluation. The first one estimates the required partial reconfiguration time based on the resources consumed by the corresponding vector kernels. The second approach uses the actual measurement of partial reconfiguration time on a platform that supports a particular type of partial reconfiguration. More than 20% performance improvement has been observed for benchmark kernels, without neglecting the reconfiguration overhead. A framework is proposed as well to efficiently manage the reconfiguration overhead for applications involving multiple kernels.

Cite this paper

APA 7

Hasan, M. Z., & Ziavras, S. G. (2007). Partially Reconfigurable Vector Processor for Embedded Applications. Journal of Computers, 2(9). https://doi.org/10.4304/jcp.2.9.60-66

MLA 9

Hasan, Muhammad Z, and Sotirios G. Ziavras. “Partially Reconfigurable Vector Processor for Embedded Applications.” Journal of Computers, vol. 2, no. 9, 2007, https://doi.org/10.4304/jcp.2.9.60-66.

Chicago

Hasan, Muhammad Z, and Sotirios G. Ziavras. 2007. “Partially Reconfigurable Vector Processor for Embedded Applications.” Journal of Computers 2 (9). https://doi.org/10.4304/jcp.2.9.60-66.

Harvard

Hasan, M.Z. and Ziavras, S.G. (2007) ‘Partially Reconfigurable Vector Processor for Embedded Applications’, Journal of Computers, 2(9). Available at: https://doi.org/10.4304/jcp.2.9.60-66.

BibTeX

@article{hasan2007partially,
  title = {{Partially Reconfigurable Vector Processor for Embedded Applications}},
  author = {Hasan, Muhammad Z and Ziavras, Sotirios G.},
  journal = {Journal of Computers},
  volume = {2},
  number = {9},
  year = {2007},
  doi = {10.4304/jcp.2.9.60-66}
}

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