article · 1986

Reconfigurable Systolic Array Implementation of

M Van Pee, Pramod P. Khargonekar, E. Bruce Lee, Hsing-Hsing Chiang, C.L. Nikias, A.N. Venetsanopoulos

Cited by 0Abstract and details only

Abstract

B( zl, z2) = 1 - z2 + 0.22; - 0.5~~ + 0.8~~~~ Abstract -In this correspondence, we present a new reconfigurable implementation structure for quadratic digital filters using systolic arrays. The structure is based on matrix decomposition realizations and exhibits high parallelism, great modularity, and regularity. It is flexible enough to accommodate any quadratic filter of a given order and rank, just by opening a number of switches and tuning a set of parameters at each active module.

Cite this paper

APA 7

Van Pee, M., Khargonekar, P. P., Lee, E. B., Chiang, H.-H., Nikias, C., & Venetsanopoulos, A. (1986). Reconfigurable Systolic Array Implementation of.

MLA 9

Van Pee, M, et al. “Reconfigurable Systolic Array Implementation of.” 1986.

Chicago

Van Pee, M, Pramod P. Khargonekar, E. Bruce Lee, Hsing-Hsing Chiang, C.L. Nikias, and A.N. Venetsanopoulos. 1986. “Reconfigurable Systolic Array Implementation of.”

Harvard

Van Pee, M. et al. (1986) ‘Reconfigurable Systolic Array Implementation of’.

BibTeX

@article{vanpee1986reconfigurable,
  title = {{Reconfigurable Systolic Array Implementation of}},
  author = {Van Pee, M and Khargonekar, Pramod P. and Lee, E. Bruce and Chiang, Hsing-Hsing and Nikias, C.L. and Venetsanopoulos, A.N.},
  year = {1986}
}

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