article · 2016

Power analysis of bit interleaving 9T SRAM array

Cited by 3Abstract and details only

Abstract

Soft error issue is major concern in SRAM array. It can be overcome if the array is constructed in bit interleaving architecture. Hence in this paper, an analysis of bit interleaving SRAM array to overcome soft error using 9T SRAM cell has been made. It shows that 9T SRAM array with bit interleaving architecture has less power and has good stability when compared to shared word line architecture using 6T SRAM cell. Area, Power and SNM has been compared for 6T SRAM and 9T SRAM. Results indicates that 9T SRAM cell shows power reduction of 75.89 % when compared to conventional 6T SRAM cell with trade - off of 25.98 % increase in area. The 9T SRAM cell also has 63.03 % improvement in SNM than 6T SRAM cell.

Cite this paper

APA 7

Karthika, S., & Sivamangai, N. M. (2016). Power analysis of bit interleaving 9T SRAM array. https://doi.org/10.1109/icdcsyst.2016.7570608

MLA 9

Karthika, S., and N. M. Sivamangai. “Power analysis of bit interleaving 9T SRAM array.” vol. 47, 2016, pp. 275–80, https://doi.org/10.1109/icdcsyst.2016.7570608.

Chicago

Karthika, S., and N. M. Sivamangai. 2016. “Power analysis of bit interleaving 9T SRAM array.” https://doi.org/10.1109/icdcsyst.2016.7570608.

Harvard

Karthika, S. and Sivamangai, N.M. (2016) ‘Power analysis of bit interleaving 9T SRAM array’. Available at: https://doi.org/10.1109/icdcsyst.2016.7570608.

BibTeX

@article{karthika2016power,
  title = {{Power analysis of bit interleaving 9T SRAM array}},
  author = {Karthika, S. and Sivamangai, N. M.},
  volume = {47},
  pages = {275--280},
  year = {2016},
  doi = {10.1109/icdcsyst.2016.7570608}
}

Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.