article · IET Circuits Devices & Systems · 2019

Three‐state dynamic random‐access memory (DRAM)

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Abstract

Abstract This work shows the design of three‐valued dynamic random‐access memory (DRAM) cell using quantum dot gate field effect transistor. DRAM is very popular for increasing device integration in integrated circuits. Storing multiple numbers of bits in a single DRAM cell increases the device integration further. The process technology is compatible with the conventional silicon process. The various write and read operations of the three‐value DRAM cell are also discussed in this work.

Cite this paper

APA 7

Karmakar, S. (2019). Three‐state dynamic random‐access memory (DRAM). IET Circuits Devices & Systems, 14(2), 176–181. https://doi.org/10.1049/iet-cds.2019.0117

MLA 9

Karmakar, Supriya. “Three‐state dynamic random‐access memory (DRAM).” IET Circuits Devices & Systems, vol. 14, no. 2, 2019, pp. 176–81, https://doi.org/10.1049/iet-cds.2019.0117.

Chicago

Karmakar, Supriya. 2019. “Three‐state dynamic random‐access memory (DRAM).” IET Circuits Devices & Systems 14 (2): 176–81. https://doi.org/10.1049/iet-cds.2019.0117.

Harvard

Karmakar, S. (2019) ‘Three‐state dynamic random‐access memory (DRAM)’, IET Circuits Devices & Systems, 14(2), pp. 176–181. Available at: https://doi.org/10.1049/iet-cds.2019.0117.

BibTeX

@article{karmakar2019three,
  title = {{Three‐state dynamic random‐access memory (DRAM)}},
  author = {Karmakar, Supriya},
  journal = {IET Circuits Devices & Systems},
  volume = {14},
  number = {2},
  pages = {176--181},
  year = {2019},
  doi = {10.1049/iet-cds.2019.0117}
}

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