article · 2020
Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator
Cited by 2Abstract and details only
Abstract
A True Random Number Generator (TRNG) using a pair of Phase-locked Loops (PLLs) or Digital Clock Managers (DCMs) has an advantage of minimal usage of logic elements of FPGA. This paper focuses on a new clocking element of Xilinx FPGAs called mixed-mode clock manager (MMCM) and presents its effective use for better randomness and higher throughput. According to an evaluation on an Artix-7 FPGA using 132 sets of parameters, 89 sets passed AIS-31 Procedure B with the proposed method, while only 9 sets passed when simply porting an existing DCM-based method. The average throughput was 1.18 Mbit/s, which was 5x faster than an existing DCM-based method.
Cite this paper
Fujieda, N., & Takashima, S. (2020). Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator. https://doi.org/10.1109/candarw51189.2020.00047
Fujieda, Naoki, and Sogo Takashima. “Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator.” 2020, pp. 197–203, https://doi.org/10.1109/candarw51189.2020.00047.
Fujieda, Naoki, and Sogo Takashima. 2020. “Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator.” https://doi.org/10.1109/candarw51189.2020.00047.
Fujieda, N. and Takashima, S. (2020) ‘Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator’. Available at: https://doi.org/10.1109/candarw51189.2020.00047.
@article{fujieda2020enhanced,
title = {{Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator}},
author = {Fujieda, Naoki and Takashima, Sogo},
pages = {197--203},
year = {2020},
doi = {10.1109/candarw51189.2020.00047}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.