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editorial · IEICE Transactions on Electronics · 1993

Speculative Execution and Reducing Branch Penalty on a Superscalar Processor (Special Issue on New Architecture LSIs)

Hideki Ando, Chikako Nakanishi, H. Machida, Tetsuya Hara, Masao Nakaya

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Abstract

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Cite this paper

APA 7

Ando, H., Nakanishi, C., Machida, H., Hara, T., & Nakaya, M. (1993). Speculative Execution and Reducing Branch Penalty on a Superscalar Processor (Special Issue on New Architecture LSIs). IEICE Transactions on Electronics, 76(7), 1080–1093.

MLA 9

Ando, Hideki, et al. “Speculative Execution and Reducing Branch Penalty on a Superscalar Processor (Special Issue on New Architecture LSIs).” IEICE Transactions on Electronics, vol. 76, no. 7, 1993, pp. 1080–93.

Chicago

Ando, Hideki, Chikako Nakanishi, H. Machida, Tetsuya Hara, and Masao Nakaya. 1993. “Speculative Execution and Reducing Branch Penalty on a Superscalar Processor (Special Issue on New Architecture LSIs).” IEICE Transactions on Electronics 76 (7): 1080–93.

Harvard

Ando, H. et al. (1993) ‘Speculative Execution and Reducing Branch Penalty on a Superscalar Processor (Special Issue on New Architecture LSIs)’, IEICE Transactions on Electronics, 76(7), pp. 1080–1093.

BibTeX
@article{ando1993speculative,
  title = {{Speculative Execution and Reducing Branch Penalty on a Superscalar Processor (Special Issue on New Architecture LSIs)}},
  author = {Ando, Hideki and Nakanishi, Chikako and Machida, H. and Hara, Tetsuya and Nakaya, Masao},
  journal = {IEICE Transactions on Electronics},
  volume = {76},
  number = {7},
  pages = {1080--1093},
  year = {1993}
}

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