article · Microprocessors and Microsystems · 1993

Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips

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Cite this paper

(1993). Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips. Microprocessors and Microsystems, 17(1), 47. https://doi.org/10.1016/0141-9331(93)90098-r

MLA 9

“Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips.” Microprocessors and Microsystems, vol. 17, no. 1, 1993, p. 47, https://doi.org/10.1016/0141-9331(93)90098-r.

Chicago

1993. “Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips.” Microprocessors and Microsystems 17 (1): 47. https://doi.org/10.1016/0141-9331(93)90098-r.

Harvard

(1993) ‘Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips’, Microprocessors and Microsystems, 17(1), p. 47. Available at: https://doi.org/10.1016/0141-9331(93)90098-r.

BibTeX

@article{anon1993fault,
  title = {{Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips}},
  journal = {Microprocessors and Microsystems},
  volume = {17},
  number = {1},
  pages = {47},
  year = {1993},
  doi = {10.1016/0141-9331(93)90098-r}
}

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