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article · IEEE Access · 2023

On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

Awais Saeed, Ubaid U. Fayyaz, Ahsan Tahir, Seokin Hong, Tayyeb Mahmood

Cited by 3Open access

Abstract

In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

Cite this paper

APA 7

Saeed, A., Fayyaz, U. U., Tahir, A., Hong, S., & Mahmood, T. (2023). On the Positional Single Error Correction and Double Error Detection in Racetrack Memories. IEEE Access, 11, 18300–18310. https://doi.org/10.1109/access.2023.3246726

MLA 9

Saeed, Awais, et al. “On the Positional Single Error Correction and Double Error Detection in Racetrack Memories.” IEEE Access, vol. 11, 2023, pp. 18300–10, https://doi.org/10.1109/access.2023.3246726.

Chicago

Saeed, Awais, Ubaid U. Fayyaz, Ahsan Tahir, Seokin Hong, and Tayyeb Mahmood. 2023. “On the Positional Single Error Correction and Double Error Detection in Racetrack Memories.” IEEE Access 11: 18300–10. https://doi.org/10.1109/access.2023.3246726.

Harvard

Saeed, A. et al. (2023) ‘On the Positional Single Error Correction and Double Error Detection in Racetrack Memories’, IEEE Access, 11, pp. 18300–18310. Available at: https://doi.org/10.1109/access.2023.3246726.

BibTeX
@article{saeed2023positional,
  title = {{On the Positional Single Error Correction and Double Error Detection in Racetrack Memories}},
  author = {Saeed, Awais and Fayyaz, Ubaid U. and Tahir, Ahsan and Hong, Seokin and Mahmood, Tayyeb},
  journal = {IEEE Access},
  volume = {11},
  pages = {18300--18310},
  year = {2023},
  doi = {10.1109/access.2023.3246726}
}

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