article · Electronics · 2024

Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments

Ho-Jin Choi, SeongJun Choi, Seog Chung Seo

Cited by 3Open access

Abstract

Currently, cryptographic hash functions are widely used in various applications, including message authentication codes, cryptographic random generators, digital signatures, key derivation functions, and post-quantum algorithms. Notably, they play a vital role in establishing secure communication between servers and clients. Specifically, servers often need to compute a large number of hash functions simultaneously to provide smooth services to connected clients. In this paper, we present highly optimized parallel implementations of Lightweight Secure Hash (LSH), a hash algorithm developed in Korea, on server sides. To optimize LSH performance, we leverage two parallel architectures: AVX-512 on high-end CPUs and NVIDIA GPUs. In essence, we introduce a word-level parallel processing design suitable for AVX-512 instruction sets and a data parallel processing design appropriate for the NVIDIA CUDA platform. In the former approach, we parallelize the core functions of LSH using AVX-512 registers and instructions. As a result, our first implementation achieves a performance improvement of up to 50.37% compared to the latest LSH AVX-2 implementation. In the latter approach, we optimize the core operation of LSH with CUDA PTX assembly and apply a coalesced memory access pattern. Furthermore, we determine the optimal number of blocks/threads configuration and CUDA streams for RTX 2080Ti and RTX 3090. Consequently, in the RTX 3090 architecture, our optimized CUDA implementation achieves about a 180.62% performance improvement compared with the initially ported LSH implementation to the CUDA platform. As far as we know, this is the first work on optimizing LSH with AVX-512 and NVIDIA GPU. The proposed implementation methodologies can be used alone or together in a server environment to achieve the maximum throughput of LSH computation.

Cite this paper

APA 7

Choi, H.-J., Choi, S., & Seo, S. C. (2024). Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments. Electronics, 13(5), 896. https://doi.org/10.3390/electronics13050896

MLA 9

Choi, Ho-Jin, et al. “Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments.” Electronics, vol. 13, no. 5, 2024, p. 896, https://doi.org/10.3390/electronics13050896.

Chicago

Choi, Ho-Jin, SeongJun Choi, and Seog Chung Seo. 2024. “Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments.” Electronics 13 (5): 896. https://doi.org/10.3390/electronics13050896.

Harvard

Choi, H.-J., Choi, S. and Seo, S.C. (2024) ‘Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments’, Electronics, 13(5), p. 896. Available at: https://doi.org/10.3390/electronics13050896.

BibTeX

@article{choi2024parallel,
  title = {{Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments}},
  author = {Choi, Ho-Jin and Choi, SeongJun and Seo, Seog Chung},
  journal = {Electronics},
  volume = {13},
  number = {5},
  pages = {896},
  year = {2024},
  doi = {10.3390/electronics13050896}
}

Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.