article · 2024

Set the Clock: A Synthesizable Clock Manager

Jonas Lienke, Florian Kögler, Eric Schäfer, Georg Gläser

Cited by 0Abstract and details only

Abstract

The design of clock management circuitry is currently done using a more or less analog design flow. For a current chip design, we show a fully-digital implementation of a digital clock manager (DCM) block that generates a clock signal from a reference clock. It utilizes a PLL-like structure for self-calibration and is implemented purely in Verilog. Since the DCM is designed only in synthesizable Verilog, it eliminates the need for an analog simulation and enabling automated synthesis and layout. We verify our circuit using a standard digital simulation method with annotated timings extracted from the layout. The DCM is implemented in a commercial 350 nm CMOS technology using $0.138 \mathrm{~mm}^{2}$. In our scenario, it creates a clock of 70 MHz from a reference clock of 5 MHz with a jitter of 30 ps.

Cite this paper

APA 7

Lienke, J., Kögler, F., Schäfer, E., & Gläser, G. (2024). Set the Clock: A Synthesizable Clock Manager. https://doi.org/10.1109/smacd61181.2024.10745390

MLA 9

Lienke, Jonas, et al. “Set the Clock: A Synthesizable Clock Manager.” 2024, pp. 1–4, https://doi.org/10.1109/smacd61181.2024.10745390.

Chicago

Lienke, Jonas, Florian Kögler, Eric Schäfer, and Georg Gläser. 2024. “Set the Clock: A Synthesizable Clock Manager.” https://doi.org/10.1109/smacd61181.2024.10745390.

Harvard

Lienke, J. et al. (2024) ‘Set the Clock: A Synthesizable Clock Manager’. Available at: https://doi.org/10.1109/smacd61181.2024.10745390.

BibTeX

@article{lienke2024clock,
  title = {{Set the Clock: A Synthesizable Clock Manager}},
  author = {Lienke, Jonas and Kögler, Florian and Schäfer, Eric and Gläser, Georg},
  pages = {1--4},
  year = {2024},
  doi = {10.1109/smacd61181.2024.10745390}
}

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