article · 2025

Integration and performance analysis of parallel RISC-V architectures

Casio P. Krebs, Guido Araújo, Lucas Wanner

Cited by 0Open access

Abstract

Vector and matrix architectures accelerate workloads by exploiting data-level parallelism and reducing instruction overhead, but using them typically requires manual code changes. This work explores the Hwacha vector coprocessor and Gemmini matrix accelerator, alongside the BOOM superscalar RISC-V core, aiming to automate their activation. The SMR code rewriting tool was extended with libraries for data preparation, movement, and Hwacha/Gemmini activation for GEMV and GEMM. Integrated with Verilator, a simulation environment evaluated performance across seven Polybench kernels. Results show SMR can activate hardware accelerators without modifying the base code, enabling efficient acceleration more easily.

Cite this paper

APA 7

Krebs, C. P., Araújo, G., & Wanner, L. (2025). Integration and performance analysis of parallel RISC-V architectures. https://doi.org/10.5753/sscad.2025.16672

MLA 9

Krebs, Casio P., et al. “Integration and performance analysis of parallel RISC-V architectures.” 2025, pp. 205–16, https://doi.org/10.5753/sscad.2025.16672.

Chicago

Krebs, Casio P., Guido Araújo, and Lucas Wanner. 2025. “Integration and performance analysis of parallel RISC-V architectures.” https://doi.org/10.5753/sscad.2025.16672.

Harvard

Krebs, C.P., Araújo, G. and Wanner, L. (2025) ‘Integration and performance analysis of parallel RISC-V architectures’. Available at: https://doi.org/10.5753/sscad.2025.16672.

BibTeX

@article{krebs2025integration,
  title = {{Integration and performance analysis of parallel RISC-V architectures}},
  author = {Krebs, Casio P. and Araújo, Guido and Wanner, Lucas},
  pages = {205--216},
  year = {2025},
  doi = {10.5753/sscad.2025.16672}
}

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