article · Greater South Information System · 2022
A novel method for on-chip debugging based on RISC-V processor
Shan Gao, Dehua Wu, Wan'ang Xiao, Zetao Wang, Zhenghong Yang, Wanlin Gao
Cited by 0Open access
Abstract
An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.
Cite this paper
Gao, S., Wu, D., Xiao, W., Wang, Z., Yang, Z., & Gao, W. (2022). A novel method for on-chip debugging based on RISC-V processor. Greater South Information System. https://doi.org/10.60692/33wde-k6r65
Gao, Shan, et al. “A novel method for on-chip debugging based on RISC-V processor.” Greater South Information System, 2022, https://doi.org/10.60692/33wde-k6r65.
Gao, Shan, Dehua Wu, Wan'ang Xiao, Zetao Wang, Zhenghong Yang, and Wanlin Gao. 2022. “A novel method for on-chip debugging based on RISC-V processor.” Greater South Information System. https://doi.org/10.60692/33wde-k6r65.
Gao, S. et al. (2022) ‘A novel method for on-chip debugging based on RISC-V processor’, Greater South Information System. Available at: https://doi.org/10.60692/33wde-k6r65.
@article{gao2022novel,
title = {{A novel method for on-chip debugging based on RISC-V processor}},
author = {Gao, Shan and Wu, Dehua and Xiao, Wan'ang and Wang, Zetao and Yang, Zhenghong and Gao, Wanlin},
journal = {Greater South Information System},
year = {2022},
doi = {10.60692/33wde-k6r65}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.