article · KiltHub Repository · 1991

Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators

Jain, Alok, Bryant, Randal E.

Cited by 0Open access

Abstract

In this paper, we present a framework for performing switch-level simulation on hardware accelerators.

Cite this paper

Jain, A., & Bryant, R. E. (1991). Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators. KiltHub Repository. https://doi.org/10.1184/r1/6607115

MLA 9

Jain, Alok, and Randal E. Bryant. “Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators.” KiltHub Repository, 1991, https://doi.org/10.1184/r1/6607115.

Chicago

Jain, Alok, and Randal E. Bryant. 1991. “Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators.” KiltHub Repository. https://doi.org/10.1184/r1/6607115.

Harvard

Jain, A. and Bryant, R.E. (1991) ‘Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators’, KiltHub Repository. Available at: https://doi.org/10.1184/r1/6607115.

BibTeX

@article{jain1991mapping,
  title = {{Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators}},
  author = {Jain, Alok and Bryant, Randal E.},
  journal = {KiltHub Repository},
  year = {1991},
  doi = {10.1184/r1/6607115}
}

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