other · LARA - Libre Acces aux Rapports scientifiques et techniques · 2006
Loop Partitioning versus Tiling for Cache-based Multiprocessors.
Laboratoire de l'informatique du parallélisme, Rastello, Fabrice, Robert, Yves
Cited by 0Abstract and details only
Abstract
(eng) In this paper, an efficient algorithm to implement loop partitioning is introduced and evaluated. We improve recent results of Agarwal, Kranz and Natarajan in several directions. We give a more accurate estimation of the cumulative footprint, and we derive a much more powerful algorithm to determine the optimal tile shape. We illustrate the superiority of our algorithm on the same examples as those of Agarwal, Kranz and Natarajan to ensure the fairness of the comparisons.
Cite this paper
du parallélisme, L. D. L., Rastello, F., & Robert, Y. (2006). Loop Partitioning versus Tiling for Cache-based Multiprocessors. LARA - Libre Acces aux Rapports scientifiques et techniques.
du parallélisme, Laboratoire de l'informatique, et al. “Loop Partitioning versus Tiling for Cache-based Multiprocessors.” LARA - Libre Acces aux Rapports scientifiques et techniques, 2006.
du parallélisme, Laboratoire de l'informatique, Fabrice Rastello, and Yves Robert. 2006. “Loop Partitioning versus Tiling for Cache-based Multiprocessors.” LARA - Libre Acces aux Rapports scientifiques et techniques.
du parallélisme, L.D.L., Rastello, F. and Robert, Y. (2006) ‘Loop Partitioning versus Tiling for Cache-based Multiprocessors’, LARA - Libre Acces aux Rapports scientifiques et techniques.
@misc{duparallelisme2006loop,
title = {{Loop Partitioning versus Tiling for Cache-based Multiprocessors.}},
author = {du parallélisme, Laboratoire de l'informatique and Rastello, Fabrice and Robert, Yves},
journal = {LARA - Libre Acces aux Rapports scientifiques et techniques},
year = {2006}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.