other · Library and Archives Canada (Government of Canada) · 1998

A reduced-power VLSI architecture for sequential decoding

Tsui, Steven

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Abstract

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Cite this paper

Tsui, S. (1998). A reduced-power VLSI architecture for sequential decoding. Library and Archives Canada (Government of Canada).

MLA 9

Tsui, Steven. “A reduced-power VLSI architecture for sequential decoding.” Library and Archives Canada (Government of Canada), 1998.

Chicago

Tsui, Steven. 1998. “A reduced-power VLSI architecture for sequential decoding.” Library and Archives Canada (Government of Canada).

Harvard

Tsui, S. (1998) ‘A reduced-power VLSI architecture for sequential decoding’, Library and Archives Canada (Government of Canada).

BibTeX

@misc{tsui1998reduced,
  title = {{A reduced-power VLSI architecture for sequential decoding}},
  author = {Tsui, Steven},
  journal = {Library and Archives Canada (Government of Canada)},
  year = {1998}
}

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