article · 2007
Kernel-based memory simulation (Extended Abstract)
D. Nagle, R. Uhlig, T. Mudge, S. Sechrest
Cited by 0Abstract and details only
Abstract
) Richard Uhlig, David Nagle, Trevor Mudge & Stuart Sechrest Department of Electrical Engineering and Computer Science University of Michigan e-mail: uhlig@eecs.umich.edu, bassoon@eecs.umich.edu This work is supported by Defense Advanced Research Projects Agency under DARPA/ARO Contract Number DAAL03-90-C-0028 and a National Science Foundation Graduate Fellowship. needed, traps can be set or cleared using page valid bits, or by installing and removing page-table entries in a software -managed TLB [1]. For cache simulation, where cache-line granularity is needed, instruction breakpoints, data breakpoints, or memory parity traps can be set [2]. Two essential features of this approach enable Tapeworm to overcome the limitations of trace-driven simulation. First, because Tapeworm processes only the infrequent case of misses, it is much faster than comparable tracedriven simulators, which consider all memory references. Second, because Tapeworm resides in the kernel of a running operating...
Cite this paper
Nagle, D., Uhlig, R., Mudge, T., & Sechrest, S. (2007). Kernel-based memory simulation (Extended Abstract).
Nagle, D., et al. “Kernel-based memory simulation (Extended Abstract).” 2007.
Nagle, D., R. Uhlig, T. Mudge, and S. Sechrest. 2007. “Kernel-based memory simulation (Extended Abstract).”
Nagle, D. et al. (2007) ‘Kernel-based memory simulation (Extended Abstract)’.
@article{nagle2007kernel,
title = {{Kernel-based memory simulation (Extended Abstract)}},
author = {Nagle, D. and Uhlig, R. and Mudge, T. and Sechrest, S.},
year = {2007}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.