article · 2007
High Code Rate Iteratively-Decodable . . .
John Lodge
Cited by 0Abstract and details only
Abstract
INTRODUCTION This paper presents design techniques and performance for forward error correction (FEC) codes formed using single-parity-bit component codes. Iteratively-decodable (e.g., "turbo" decodable) codes constructed using only single-parity-bit component codes have been investigated by a number of researchers in the past; for example [1,2,3,4]. This class of codes is particularly well suited to high coderate applications, as compared to turbo-codes [5], which excel at low to moderate code rates. Furthermore, the highly parallel nature and the simple component code decoders allow very high-speed implementation. For example, using the Galaxy product of Advanced Hardware Architectures Inc., HyperCodes [3] can be implemented at data rates in excess of the OC-3 rate of 155 Mbps. However, similar to turbo-codes, this class of codes can experience a "flattening" or "flaring" of the bit-error rate curve at high signal-to-noise ratios (SNR) that limits the ultimate power efficiency
Cite this paper
Lodge, J. (2007). High Code Rate Iteratively-Decodable . . .
Lodge, John. “High Code Rate Iteratively-Decodable . . .” 2007.
Lodge, John. 2007. “High Code Rate Iteratively-Decodable . . .”
Lodge, J. (2007) ‘High Code Rate Iteratively-Decodable . . ’.
@article{lodge2007high,
title = {{High Code Rate Iteratively-Decodable . . .}},
author = {Lodge, John},
year = {2007}
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