article · 1996

Static Scheduling of Instructions on Micronet-based Asynchronous Processors

Arvind And Rebello, D. K. Arvind, V. E. F. Rebello

Cited by 0Abstract and details only

Abstract

This paper investigates issues which impinge on the design of static instruction schedulers for micronetbased asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers.

Cite this paper

APA 7

Rebello, A. A., Arvind, D. K., & Rebello, V. E. F. (1996). Static Scheduling of Instructions on Micronet-based Asynchronous Processors.

MLA 9

Rebello, Arvind And, et al. “Static Scheduling of Instructions on Micronet-based Asynchronous Processors.” 1996.

Chicago

Rebello, Arvind And, D. K. Arvind, and V. E. F. Rebello. 1996. “Static Scheduling of Instructions on Micronet-based Asynchronous Processors.”

Harvard

Rebello, A.A., Arvind, D.K. and Rebello, V.E.F. (1996) ‘Static Scheduling of Instructions on Micronet-based Asynchronous Processors’.

BibTeX

@article{rebello1996static,
  title = {{Static Scheduling of Instructions on Micronet-based Asynchronous Processors}},
  author = {Rebello, Arvind And and Arvind, D. K. and Rebello, V. E. F.},
  year = {1996}
}

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