article · 2001
Micronet-based CISC Architectures
Arvind And Bainbridge, D. K. Arvind, C. Bainbridge
Cited by 0Abstract and details only
Abstract
We have in the past investigated the design and implementation of micronet-based architectures of the scalar[AR94], superscalar[AM99], VLIW[AS97] and Multithreaded[AHKR01] kind, which were all based on a RISC-like instruction set. In this paper, we present a preliminary design, based around a micronet core, of an asynchronous Complex Instruction Set Computer (CISC) architecture. A TRANSLATOR module converts the CISC instructions into ones which are native to the micronet datapath, called the milliops instructions. This translation can be accomplished either in hardware, as in Intel's x86 architectures, or in software, in the style of Transmeta's Crusoe architecture. The design environment enables C programs targeted at the CISC architecture, to be executed on a RTL model of the micronet core, and its execution and power consumption can be visualised over space and time. This allows a systematic study of the effect of compiler and architectural optimisations of micronet-based CISC processors, on the performance of application benchmarks.
Cite this paper
Bainbridge, A. A., Arvind, D. K., & Bainbridge, C. (2001). Micronet-based CISC Architectures.
Bainbridge, Arvind And, et al. “Micronet-based CISC Architectures.” 2001.
Bainbridge, Arvind And, D. K. Arvind, and C. Bainbridge. 2001. “Micronet-based CISC Architectures.”
Bainbridge, A.A., Arvind, D.K. and Bainbridge, C. (2001) ‘Micronet-based CISC Architectures’.
@article{bainbridge2001micronet,
title = {{Micronet-based CISC Architectures}},
author = {Bainbridge, Arvind And and Arvind, D. K. and Bainbridge, C.},
year = {2001}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.