article · 1995

C-NNAP: An Architecture for the Parallel Processing of Binary Neural Networks

John V. Kennedy, Jim Austin, Rick Pack, Bruce Cass

Cited by 0Abstract and details only

Abstract

This paper describes the C-NNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. C-NNAP comprises an array of VME cards each containing a DSP, SCSI controller and the SAT peripheral processor. The SAT processor is a dedicated hardware implementation that performs binary neural network computations. The SAT processor yields a speed-up of greater than 180 times over the current DSP with its dedicated coprocessor. C-NNAP in association with the SAT processor provide a fast, parallel environment for performing binary neural network operations. 1. Introduction Binary neural networks based on the N-tuple method [6] have been used in image processing for pig evisceration [1], scene analysis [5] and they also have potential for use in knowledge manipulation [3]. However, an obstacle to the use of binary neural networks in real-time image processing systems is the requirement to process large quantities of data. The binary neur...

Cite this paper

APA 7

Kennedy, J. V., Austin, J., Pack, R., & Cass, B. (1995). C-NNAP: An Architecture for the Parallel Processing of Binary Neural Networks.

MLA 9

Kennedy, John V., et al. “C-NNAP: An Architecture for the Parallel Processing of Binary Neural Networks.” 1995.

Chicago

Kennedy, John V., Jim Austin, Rick Pack, and Bruce Cass. 1995. “C-NNAP: An Architecture for the Parallel Processing of Binary Neural Networks.”

Harvard

Kennedy, J.V. et al. (1995) ‘C-NNAP: An Architecture for the Parallel Processing of Binary Neural Networks’.

BibTeX

@article{kennedy1995nnap,
  title = {{C-NNAP: An Architecture for the Parallel Processing of Binary Neural Networks}},
  author = {Kennedy, John V. and Austin, Jim and Pack, Rick and Cass, Bruce},
  year = {1995}
}

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