article · 2007

SDRAM with OPB Central DMA

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Abstract

This application note describes a reference system that demonstrates the use of the Multi-CHannel (MCH) On-chip Peripheral Bus (OPB) Double Data Rate (DDR) Synchronous DRAM (SDRAM) controller in a MicroBlaze ™ processor system. Two MCH ports of the MCH OPB DDR SDRAM controller are connected to the cache ports of the MicroBlaze processor. The ports are configured with the Xilinx Cachelink (XCL) protocol which allows for efficient cacheline accesses by the processor. The OPB Central DMA controller is included in this system to generate OPB sequential address (burst) transactions. The software application provided with this reference system tests the capability of the MCH OPB DDR SDRAM core to handle cacheline accesses from the MicroBlaze processor and OPB burst transactions from the OPB Central DMA controller. The MCH OPB DDR SDRAM controller can be implemented on Virtex™-II Pro, Spartan™-3, and Virtex-4 FPGAs with boards that support DDR SDRAM. This application note describes how to set up MicroBlaze parameters for caching, the clocking structure for the MCH OPB DDR SDRAM, and parameters for OPB burst transactions from the OPB Central DMA controller. This reference system is targeted for the Xilinx SP305 Spartan-3

Cite this paper

APA 7

(2007). SDRAM with OPB Central DMA.

MLA 9

“SDRAM with OPB Central DMA.” 2007.

Chicago

2007. “SDRAM with OPB Central DMA.”

Harvard

(2007) ‘SDRAM with OPB Central DMA’.

BibTeX

@article{anon2007sdram,
  title = {{SDRAM with OPB Central DMA}},
  year = {2007}
}

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