article · 2014

Reconfigurable RISC Processor Design and Implementation

Prathamesh Berde, Dr. R. D. Daruwala, Sachin Kharude

Cited by 0Abstract and details only

Abstract

For any computing process we have to perform specific operations in sequence so as to operate and process the data in required sequence. The basic motto here is to design implement &amp; evaluate the reconfigurable processor. It is uses software hardware co-design environment. This reconfigurable processor works similarly like special purpose processors but at much lesser cost than in compared to them as the cost of the processor is important aspect in designing any system. The components are designed in VHDL in top level architecture. It is simulated and synthesized using Active HDL/Xilinx foundation series.

Cite this paper

APA 7

Berde, P., Daruwala, D. R. D., & Kharude, S. (2014). Reconfigurable RISC Processor Design and Implementation.

MLA 9

Berde, Prathamesh, et al. “Reconfigurable RISC Processor Design and Implementation.” 2014.

Chicago

Berde, Prathamesh, Dr. R. D. Daruwala, and Sachin Kharude. 2014. “Reconfigurable RISC Processor Design and Implementation.”

Harvard

Berde, P., Daruwala, D.R.D. and Kharude, S. (2014) ‘Reconfigurable RISC Processor Design and Implementation’.

BibTeX

@article{berde2014reconfigurable,
  title = {{Reconfigurable RISC Processor Design and Implementation}},
  author = {Berde, Prathamesh and Daruwala, Dr. R. D. and Kharude, Sachin},
  year = {2014}
}

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