article · 1999

Layout-driven Logic Optimization

Carragher Murgai Chakraborty, R. Carragher, R. Murgai, S. Chakraborty, M. R. Prasad, A. Srivastava, N. Vemuri

Cited by 0Abstract and details only

Abstract

With the advent of deep sub-microntechnologies, interconnect loads and delays are becoming dominant. Consequently, the currently used design flow of iteratively performing logic synthesis with statistical wire-load models, doing placement &amp; routing, extracting parasitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. In this paper, we present a layout-driven optimization methodology that incorporates logic-level transformations for improving the delay and area of a mapped, block-placed, and globally routed design under certain constraints such as area availability, congestion, hold-time, and pin drive, etc. We argue that this is the right stage for optimization. Only those transformations that are local, incremental, and layout-friendly are incorporated. Examples of such transformations are net buffering, gate resizing, generalized DeMorgan transform, and pin permutation. We propose a sim...

Cite this paper

APA 7

Chakraborty, C. M., Carragher, R., Murgai, R., Chakraborty, S., Prasad, M. R., Srivastava, A., & Vemuri, N. (1999). Layout-driven Logic Optimization.

MLA 9

Chakraborty, Carragher Murgai, et al. “Layout-driven Logic Optimization.” 1999.

Chicago

Chakraborty, Carragher Murgai, R. Carragher, R. Murgai, S. Chakraborty, M. R. Prasad, A. Srivastava, and N. Vemuri. 1999. “Layout-driven Logic Optimization.”

Harvard

Chakraborty, C.M. et al. (1999) ‘Layout-driven Logic Optimization’.

BibTeX

@article{chakraborty1999layout,
  title = {{Layout-driven Logic Optimization}},
  author = {Chakraborty, Carragher Murgai and Carragher, R. and Murgai, R. and Chakraborty, S. and Prasad, M. R. and Srivastava, A. and Vemuri, N.},
  year = {1999}
}

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