article · 2006

Microarchitecture-Independent Snapshots

Kenneth C. Barr, Krste Asanović, Kenneth C. Barr

Cited by 0Abstract and details only

Abstract

Computer architects rely heavily on software simulation to evaluate, refine, and validate new designs before they are implemented. However, simulation time continues to increase as computers become more complex and multicore designs become more common. This thesis investigates software structures and algorithms for quickly simulating modern cache-coherent multiprocessors by amortizing the time spent to simulate the memory system and branch predictors. The Memory Timestamp Record (MTR) summarizes the directory and cache state of a multiprocessor system in a compact data structure. A single MTR snapshot is versatile enough to reconstruct the microarchitectural state resulting from various coherence protocols and cache organizations. The MTR may be quickly updated by each simulated processor during a fast-forwarding phase and optionally stored off-line for reuse. To fill large branch prediction tables, we introduce Branch Predictor-based Compression (BPC) which compactly stores a branch trace so that it may be used to fill in any branch predictor structure. An entire BPC trace requires less space than single discrete predictor

Cite this paper

APA 7

Barr, K. C., Asanović, K., & Barr, K. C. (2006). Microarchitecture-Independent Snapshots.

MLA 9

Barr, Kenneth C., et al. “Microarchitecture-Independent Snapshots.” 2006.

Chicago

Barr, Kenneth C., Krste Asanović, and Kenneth C. Barr. 2006. “Microarchitecture-Independent Snapshots.”

Harvard

Barr, K.C., Asanović, K. and Barr, K.C. (2006) ‘Microarchitecture-Independent Snapshots’.

BibTeX

@article{barr2006microarchitecture,
  title = {{Microarchitecture-Independent Snapshots}},
  author = {Barr, Kenneth C. and Asanović, Krste and Barr, Kenneth C.},
  year = {2006}
}

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