article · 2008

Statistical Static Timing Analysis and Optimization

Narendra Shenoy

Cited by 0Abstract and details only

Abstract

Circuit design needs to account for variability in process and operating conditions in order to manufacture a reasonable ratio of functional chips to total fabricated chips. This ratio is often termed as the “yield ” of a design. Traditionally, this has been achieved by providing margins for the worst-case scenario during the design process. Unfortunately this makes an implicit assumption that there is a single worst-case assignment to process parameters and operating conditions. Secondly, this can lead to severe over design in terms of area and power. As technology scales, the effect of variability on circuit behavior increases. This project aims to 1. Develop fast statistical timing analysis technology for use during optimization 2. Define a timing yield metric and design an optimization strategy to improve the timing yield 3. Compare timing yield in the traditional worst-case design methodology to a design methodology that accommodates variability Details The statistical models for gate delays are built by examining the delay behavior of the

Cite this paper

APA 7

Shenoy, N. (2008). Statistical Static Timing Analysis and Optimization.

MLA 9

Shenoy, Narendra. “Statistical Static Timing Analysis and Optimization.” 2008.

Chicago

Shenoy, Narendra. 2008. “Statistical Static Timing Analysis and Optimization.”

Harvard

Shenoy, N. (2008) ‘Statistical Static Timing Analysis and Optimization’.

BibTeX

@article{shenoy2008statistical,
  title = {{Statistical Static Timing Analysis and Optimization}},
  author = {Shenoy, Narendra},
  year = {2008}
}

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