dataset · Zenodo (CERN European Organization for Nuclear Research) · 2025

Mini Risc v processor ( ALU+ Register module)

Dr.k.R.Remya (project Head), Udhaya.R, Nithikkannan.J.S ,Ajaikumar.G ,Mukilan.R(Team)

Cited by 0Open access

Abstract

This paper presents the design and implementation of an 8-bit Mini RISC-V processor featuring an optimized Arithmetic Logic Unit (ALU) and a compact register block architecture suitable for low-power embedded applications. The processor is developed using modular HDL design principles to ensure scalability, reusability, and ease of verification. The ALU supports fundamental arithmetic and logical operations, including addition, subtraction, AND, OR, NOT, XOR, multiplication, and division, enabling a wide range of computational tasks. A 4-register, 8-bit register file is incorporated to provide efficient data storage and retrieval for instruction execution. The proposed architecture is simulated and verified using industry-standard EDA tools, ensuring correctness, functional stability, and timing reliability. Experimental results confirm the correct operation of all modules and demonstrate successful integration of the ALU and register block into a unified processor design. This lightweight and resource-efficient Mini RISC-V processor serves as an ideal solution for academic prototyping, teaching processors, digital design laboratories, and small-scale IoT applications.

Cite this paper

APA 7

Dr.k.R.Remya (project Head), U. N. A. M. (2025). Mini Risc v processor ( ALU+ Register module). Zenodo (CERN European Organization for Nuclear Research). https://doi.org/10.5281/zenodo.17688193

MLA 9

Dr.k.R.Remya (project Head), Udhaya.R, Nithikkannan.J.S ,Ajaikumar.G ,Mukilan.R(Team). “Mini Risc v processor ( ALU+ Register module).” Zenodo (CERN European Organization for Nuclear Research), 2025, https://doi.org/10.5281/zenodo.17688193.

Chicago

Dr.k.R.Remya (project Head), Udhaya.R, Nithikkannan.J.S ,Ajaikumar.G ,Mukilan.R(Team). 2025. “Mini Risc v processor ( ALU+ Register module).” Zenodo (CERN European Organization for Nuclear Research). https://doi.org/10.5281/zenodo.17688193.

Harvard

Dr.k.R.Remya (project Head), U.N.A.M. (2025) ‘Mini Risc v processor ( ALU+ Register module)’, Zenodo (CERN European Organization for Nuclear Research). Available at: https://doi.org/10.5281/zenodo.17688193.

BibTeX

@misc{drkrremyaprojecthead2025mini,
  title = {{Mini Risc v processor ( ALU+ Register module)}},
  author = {Dr.k.R.Remya (project Head), Udhaya.R, Nithikkannan.J.S ,Ajaikumar.G ,Mukilan.R(Team)},
  journal = {Zenodo (CERN European Organization for Nuclear Research)},
  year = {2025},
  doi = {10.5281/zenodo.17688193}
}

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