Varghese George · 2008
The domain of Field-Programmable Gate Arrays (FPGAs) has undergone a dramatic revolution in the past decade. What started as a cheap alternative to custom design for implementing non-critical functions has now progressed into a new model of computation. The programmability of the device at a bit level combined with an application specific flow of data between operations offer the silicon reusability of general purpose processor with the implementation efficiency of application specific integrated circuits. One of the major drawbacks of FPGAs that has not been addressed is the poor energy efficiency. This factor has excluded the full utilization of its potential in energy sensitive domains like portable computing. Even the application domains that do not require low energy consumption will feel the consequence as the process technology moves into the sub-0.1µm region. This is because of the higher frequencies and larger chips that will be seen in the future process technologies.
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Yota Yamamoto · 2023
Cited by 1
Anthony B. Sanders, Kenneth A. LaBel, J.F. McCabe et al. · NASA Technical Reports Server (NASA) · 2004
Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.
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Next Move Strategy Consulting · Zenodo (CERN European Organization for Nuclear Research) · 2025
The global FPGA market, valued at USD 9.06 billion in 2023, is projected to reach USD 18.55 billion by 2030, growing at a CAGR of 10.5%. This growth is driven by increasing adoption across automotive, AI, IoT, data centers, and telecommunication sectors. To access the full report, visit - https://www.nextmsc.com/report/field-programmable-gate-array-fpga-market
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Next Move Strategy Consulting · Zenodo (CERN European Organization for Nuclear Research) · 2025
The global FPGA market, valued at USD 9.06 billion in 2023, is projected to reach USD 18.55 billion by 2030, growing at a CAGR of 10.5%. This growth is driven by increasing adoption across automotive, AI, IoT, data centers, and telecommunication sectors. To access the full report, visit - https://www.nextmsc.com/report/field-programmable-gate-array-fpga-market
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Michael J. Stepaniak, Maarten Uijt de Haag, Frank van Graas · 2008
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Christian C Mbaocha, Constance Kalu · 2015
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Whisnant, Hannah K. · DSpace@MIT (Massachusetts Institute of Technology) · 2020
Thesis: S.M. in Technology and Policy, Massachusetts Institute of Technology, School of Engineering, Institute for Data, Systems, and Society, Technology and Policy Program, September, 2020
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2005
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Fatema Akter, Tamanna Tabassum, Mohammed Nasir Uddin · Lecture notes in networks and systems · 2024
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Michael J. Stepaniak, Maarten Uijt de Haag, Frank van Graas · Journal of Aerospace Computing Information and Communication · 2009
Abstract : A system for determining vehicle attitude using a field programmable gate array (FPGA) and low cost gyroscopes is presented. The method is intended to support the stabilization of a short duration, unmanned aerial vehicle. Using a microelectronmechanical system (MEMS) inertial sensor for the calibration and serial interface, the algorithm sidesteps concerns related to electronmagnetic interference and the impact of embedded, proprietary filters. An Allan variance analysis is used to characterize the sensor errors and predict system performance. A floating point representation using a direction cosine matrix is hosted on the FPGA alongside the platform stabilization feedback loops. Although prone to drifting without additional aiding, the derived attitude has been demonstrated to be effective in stabilizing a remotely piloted quadrotor.
Cited by 4
Brian Box · 2002
Custom hardware implementations of preprocessors are seldom reusable, flexible enough to allow algorithm exploration or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Recent developments in FPGA hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibility possible. The key advancements are larger, faster RAM and electrically erasable devices, routers with deadline timers, and synthesis tools which can work with user-definable macros. Ongoing work in the areas of partitioning, synthesis, placement, packaging and compilation will make reconfigurable preprocessors more powerful. The present CHAMP implementation is based on Xilinx FPGAs. Its architecture consists of multiple reconfigurable processing elements connected through both a ring network and a global crossbar network. It is packaged as a VME 6U/spl times/160 slave board with two high-speed reconfigurable parallel interfaces. In order to allow development at the algorithm level while retaining preprocessor performance, off-the-shelf development tools have been integrated with a custom library of macros as part of the CHAMP design process. As a verification of the CHAMP technology, an advanced IR missile warning application was mapped onto the CHAMP architecture achieving greater than 1 billion operations/sec of real-time throughput while utilizing 75% of the CHAMP board's processing resources.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Leo Selavo, Steven P. Levitan, Donald M. Chiarulli · Optics in Computing · 1999
We have developed an optically reconfigurable field programmable gate array (OFPGA). The OFPGA integrated circuit is designed for high-speed configuration in systems based on a reconfigurable computing paradigm [1].
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A. P. Y. Phang, R.E. Challis, V. Ivchenko et al. · Measurement Science and Technology · 2008
This paper describes a novel architecture for a low-voltage ultrasonic data acquisition system intended for process monitoring of liquid chemicals in an industrial context. The system is appropriate for operations in hazardous environments where limits are imposed on the working voltage levels of equipment, due to potential fire or explosion hazards. High SNRs in the captured signal records were achieved using 1 V Golay complementary sequences combined with cross-correlation for signal detection, all of which were implemented on a single-field programmable gate array chip. The system has an operating bandwidth of 40 MHz and a dynamic range at the receiver of 2 Vp-p with a resolution of 14 bits. Theoretical and practical design criteria are examined to optimize received signal SNR and data acquisition rate whilst minimizing hardware complexity. The system was implemented using a reconfigurable hardware platform of relatively low cost, providing a basis for developing more powerful and robust systems in future. Experiments show that the performance of the system is equivalent to that of a conventional high-voltage pulse-transmission system.
Cited by 8
Yuya Isaka, Michihiro Shintani, Foisal Ahmed et al. · IEEE Transactions on Device and Materials Reliability · 2022
With the expansion of the semiconductor supply chain, the use of recycled field-programmable gate arrays (FPGAs) has become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the known fresh FPGAs (KFFs) as the training data in machine-learning-based classification. In this study, we propose a novel recycled FPGA detection method based on an unsupervised anomaly detection scheme when there are few or no KFFs available. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes recycled FPGAs from 35 fresh FPGAs. In contrast, a conventional recycled FPGA detection method results in certain misclassification.
Cited by 2Open access
Pallavi Sahay, Avinash Kumar Singh -, Diksha Sahay - · International Journal For Multidisciplinary Research · 2024
Edges are significant local changes in the image and are very important features for analysing images. Edges typically occur on the boundary between two different regions in an image. An edge in an image is a significant local change in the image intensity, usually associated with a discontinuity in either the image intensity or the first derivative of the image intensity. Edge detection is one of the tools that can be used in many image processing applications for withdrawing information from image. Sobel edge detection is one of the operators that operate on gradient based edge selection methods to find edge pixels in the image. This report proposed an implementation of Sobel edge Detection algorithm to find the pixels in grayscale images. We present a video streaming architecture and IP implementation using high level synthesis. A video with 720p resolution streamed from the HDMI source and real time edge detected video captured on another monitor. For implementation, ZYBO board or kit is used with Vivado software with 2018.3 V, which has provided adequate peripherals for implementation.
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A. Al-marakeby · 2014
Many optimization problems have complex search space, which either increase the solving problem time or finish searching without obtaining the best solution. Genetic Algorithm (GA) is an optimization technique used in solving many practical problems in science, engineering, and business domains. Parallel Genetic Algorithm (PGA) has been widely used to increase speed of GA, especially after the spread of parallel platforms such as GPUs, FPGA, and Multi-Core Processors. In this paper, we introduce a type of PGA called Fine-grained Parallel Genetic Algorithm, which has the advantages of maintaining better population diversity, and inhibiting premature. Fine-grained PGA is implemented on Field Programmable Gate Array, and the system is used to solve the classical TSP problem. The results show the advantages of the Fine-grained PGA over sequential GA, and the advantages of Field Programmable Gate Array as a parallel platform.
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Muhammed Ihsan Husni, Mohammed Kareem Hussein, Mohd Shamian Bin Zainal, Shipun Anuar Bin Hamzah, Danial Bin Md Nor, Hazwaj Bin Mhd Poad · Bulletin of Miscellaneous Information (Royal Gardens Kew) · 2018
This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turned on as the system senses the reduction in moisture content. The system implementation on hard wave level show promising results and have been discussed in detailed.
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Juan Ruiz-Rosero, Gustavo Ramírez-González, Rahul Khanna · Computation · 2019
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.
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Isaka, Yuya, Shintani, Michihiro, Ahmed, Foisal et al. · arXiv (Cornell University) · 2022
With the expansion of the semiconductor supply chain, the use of recycled field-programmable gate arrays (FPGAs) has become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the known fresh FPGAs (KFFs) as the training data in machine-learning-based classification. In this study, we propose a novel recycled FPGA detection method based on an unsupervised anomaly detection scheme when there are few or no KFFs available. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes recycled FPGAs from 35 fresh FPGAs. In contrast, a conventional recycled FPGA detection method results in certain misclassification.
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