John Nickolls, William J. Dally · IEEE Micro · 2010
GPU computing is at a tipping point, becoming more widely used in demanding consumer applications and high-performance computing. This article describes the rapid evolution of GPU architectures-from graphics processors to massively parallel many-core multiprocessors, recent developments in GPU computing architectures, and how the enthusiastic adoption of CPU+GPU coprocessing is accelerating parallel applications.
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Openanalytics Bvba, Willem Ligtenberg · 2012
Modern CPUs currently have 4 to 8 cores. In contrast an affordable GPU ( 200 euro) has 384 cores. This makes them ideally suited for parallel processing. Examples of problems that can benefit from processing on the GPU are Fast Fourier Transforms, the k-nearest neighbour algorithm or sequence alignment. If the problem can be cut into small pieces, it might be interesting to port it to the GPU. In order to make this compute power more accessible there a few options. One is to make some of the basic R functionality use the GPU directly, a second option is to wrap C(++) applications that make use of the GPU with R. Finally, we can build an interface between R and OpenCL, which leaves all possibilities open for the user and therefore provides maximum flexibility. In the first part of our presentation we will provide an overview of current R packages that use the GPU. In the second part, we will present our progress on the ROpenCL package. ROpenCL provides functions to transfer data frames to and from the GPU and to push kernel functions to the GPU, thereby unlocking the full potential of the GPU. These kernel functions still need to be written in OpenCL, however the interfacing with the GPU can all be done with R. The ROpenCL package is similar in spirit and based on the PyOpenCL
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CUHK Digital Repository (Chinese University of Hong Kong) · 2007
Real-time performance is necessary for video-rate processing. By utilizing GPU for acceleration, we propose an efficient technique for the warped display of surveillance video signal. Usually, there are regions of interest (ROIs) in video surveillance, such as entrance or exit, and moving objects or persons. The ii surveillant wants to see more of the ROIs, but also wants to have an overview of the whole surveillance scope. The warped display solves this conflict by locally zooming in the ROIs.
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Pleiter, Dirk · JuSER (Forschungszentrum Jülich) · 2012
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Johan Simon Seland · BIBSYS Brage (BIBSYS (Norway)) · 2007
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Eric M. Aldrich · Handbook of computational economics · 2014
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Kenneth Stenkjær Pedersen, G Bunker · Journal of Physics Conference Series · 2013
Modern graphics processing units (GPUs) are powerful parallel computers. Porting the mathematically intense, parallelizable algorithms of XAFS to run on GPUs should expand the scale of tractable XAFS calculations. Part of a time-limiting subroutine in FEFF 8.4 (fms) was converted to run on a GPU, showing significant performance gains. With parallel CPUs sharing GPU resources, the runtime of the modules calling fms should accelerate by one or two orders of magnitude versus a single-threaded CPU process (at least for large atomic clusters,). New or existing XAFS algorithms and programs (e.g. FEFF 9) should show similar acceleration when ported to GPUs, as long as they meet certain criteria (outlined in detail).
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Sreeram Potluri, Devendar Bureddy, Huamin Wang et al. · 2013
Graphics Processing Units (GPUs) are becoming an integral part of modern supercomputer architectures due to their high compute density and performance per watt. In order to maximize utilization, it is imperative that applications running on these clusters have low synchronization and communication overheads. Partitioned Global Address Space (PGAS) models provide an attractive approach for developing parallel scientific applications. Such models simplify programming through the abstraction of a shared memory address space while their one-sided communication primitives allow for efficient implementation of applications with minimum synchronization. OpenSHMEM is a library-based programming model that is gaining popularity. However, the current OpenSHMEM standard does not support direct communication from GPU device buffers. It requires data to be copied to the host memory before OpenSHMEM calls can be made. Similarly, data has to moved to the GPU explicitly by remote processes. This severely limits the programmability and performance of GPU applications. In this paper we provide extensions to the OpenSHMEM model which allow communication calls to be made directly on the GPU memory. The proposed extensions are interoperable with the two most popular GPU programming frameworks: CUDA and OpenCL. We present designs for an efficient OpenSHMEM runtime which transparently provide high-performance communication between GPUs in different inter-node and intra-node configurations. To the best of our knowledge this is the first work that enables GPU-GPU communication using the OpenSHMEM model for both CUDA and OpenCL computing frameworks. The proposed extensions to OpenSHMEM, coupled with the high-performance runtime, improve the latency of GPU-GPU shmem getmem operation by 90%, 40% and 17%, for intra-IOH (I/O Hub), inter-IOH and inter-node configurations. It improves the performance of OpenSHMEM atomics by up to 55% and 52%, for intra-IOH and inter-node GPU configurations respectively. The proposed enhancements improve the performance of Stencil2D kernel by 65% on a cluster of 192 GPUs and the performance of BFS kernel by 12% on a cluster of 96 GPUs.
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Justin Y. Shi, Moussa Taifi, Abdallah Khreishah et al. · 2011
General purpose GPU (GPGPU) computing has produced the fastest running supercomputers in the world. For continued sustainable progress, GPU computing at scale also need to address two open issues: a) how increase applications mean time between failures (MTBF) as we increase supercomputer's component counts, and b) how to minimize unnecessary energy consumption. Since energy consumption is defined by the number of components used, we consider a sustainable high performance computing (HPC) application can allow better performance and reliability at the same time when adding computing or communication components. This paper reports a two-tier semantic statistical multiplexing framework for sustainable HPC at scale. The idea is to leverage the powers of statistic multiplexing to tame the nagging HPC scalability challenges. We include the theoretical model, sustainability analysis and computational experiments with automatic system level multiple CPU/GPU failure containment. Our results show that assuming three times slowdown of the statistical multiplexing layer, for an application using 1024 processors with 35% checkpoint overhead, the two-tier framework will produce sustained time and energy savings for MTBF less than 6 hours. With 5% checkpoint overhead, 1.5 hour MTBF would be the break even point. These results suggest the practical feasibility for the proposed two-tier framework.
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Hwu, Wen-mei W · CERN Document Server (European Organization for Nuclear Research) · 2011
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Zanden, Van Der, Tom C, Bodlaender, HL Hans · Data Archiving and Networked Services (DANS) · 2017
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Weidong Sun, Zongmin Ma · 2009
Counting sort is a simple, stable and efficient sort algorithm with linear running time, which is a fundamental building block for many applications. This paper depicts the design issues of a data parallel implementation of the count sort algorithm on a commodity multiprocessor GPU using the Compute Unified Device Architecture (CUDA) platform, both from NVIDIA Corporation. The full parallel version runs much faster than any serial implementation on CPU with the loss of stability due to the limitation of the massive threads parallel model. But the thread-level parallel implementation still provides an efficient parallel sort primitive for many applications, which do not require stable sort or can be adapted for unstable subroutines.
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M.E. Dondorp · Research Repository (Delft University of Technology) · 2016
This report has been written to serve as an introduction to the basics of GPU computing for mechanical engineers working in the field of structural optimization. In this work, the ability of GPUs to reduce the computation time of topology optimization problems is investigated. The programming paradigm of data parallel computing is introduced. GPU programming particulars are discussed and architectural differences between CPU and GPU processors are highlighted. It is shown how linear algebra operations can be judged on their suitability towards a massively parallelmode of execution. Algorithms with a high computational intensity and regular memory access patternswill benefit the most from a parallel implementation on a GPU. The flexibility of the Python programming language may alleviate much of the difficulties of GPU programing. It is investigated if a hybrid Python/GPU framework is a feasible way of GPU computing in the context of structural optimization. Several ways to interface the GPU from Python are discussed. It is shown that it is possible to execute linear algebra operations on the GPU from a Python context and good performance is possible. However, it is observed that interprocessor communication deteriorates the overall speedup if just one operation is to be accelerated. As a guidance problem, a topology optimization compliance minimization study is introduced. The theoretical framework is given and broken down into a chain of compute steps. By profiling a conventional implementation of topology optimization, it is shown that the solver dominates the computation time entirely. Iterative solvers for linear systems are discussed in the context of topology optimization. By preconditioning the system of equations, the required amount of iterations to solve the system can be reduced. Some GPU compatible preconditioning techniques are discussed. For a topology optimization problem, a Sparse Approximate Inverse preconditioner is found to perform best. Two available conjugate gradient solver implementations have been put to the test. It is shown that, on commodity hardware, an off the shelf conjugate gradient solver for the GPU can yield a speedup compared to a competitive off the shelf conjugate gradient solver for the CPU. For a topology optimization problem, a speedup of two has been observed.
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Ashutosh Pattnaik, Xulong Tang, Onur Kayıran et al. · 2019
Data transfer overhead between computing cores and memory hierarchy has been a persistent issue for von Neumann architectures and the problem has only become more challenging with the emergence of manycore systems. A conceptually powerful approach to mitigate this overhead is to bring the computation closer to data, known as Near Data Computing (NDC). Recently, NDC has been investigated in different flavors for CPU-based multicores, while the GPU domain has received little attention. In this paper, we present a novel NDC solution for GPU architectures with the objective of minimizing on-chip data transfer between the computing cores and Last-Level Cache (LLC). To achieve this, we first identify frequently occurring Load-Compute-Store instruction chains in GPU applications. These chains, when offloaded to a compute unit closer to where the data resides, can significantly reduce data movement. We develop two offloading techniques, called LLC-Compute and Omni-Compute. The first technique, LLC-Compute, augments the LLCs with computational hardware for handling the computation offloaded to them. The second technique (Omni-Compute) employs simple bookkeeping hardware to enable GPU cores to compute instructions offloaded by other GPU cores. Our experimental evaluations on nine GPGPU workloads indicate that the LLC-Compute technique provides, on an average, 19% performance improvement (IPC), 11% performance/watt improvement, and 29% reduction in on-chip data movement compared to the baseline GPU design. The Omni-Compute design boosts these benefits to 31%, 16% and 44%, respectively.
Cited by 40Open access
Gu, Zhongshu, Valdez, Enriquillo, Ahmed, Salman et al. · arXiv (Cornell University) · 2025
GPU Confidential Computing (GPU-CC) was introduced as part of the NVIDIA Hopper Architecture, extending the trust boundary beyond traditional CPU-based confidential computing. This innovation enables GPUs to securely process AI workloads, providing a robust and efficient solution for handling sensitive data. For end users, transitioning to GPU-CC mode is seamless, requiring no modifications to existing AI applications. However, this ease of adoption contrasts sharply with the complexity of the underlying proprietary systems. The lack of transparency presents significant challenges for security researchers seeking a deeper understanding of GPU-CC's architecture and operational mechanisms. The challenges of analyzing the NVIDIA GPU-CC system arise from a scarcity of detailed specifications, the proprietary nature of the ecosystem, and the complexity of product design. In this paper, we aim to demystify the implementation of NVIDIA GPU-CC system by piecing together the fragmented and incomplete information disclosed from various sources. Our investigation begins with a high-level discussion of the threat model and security principles before delving into the low-level details of each system component. We instrument the GPU kernel module -- the only open-source component of the system -- and conduct a series of experiments to identify the security weaknesses and potential exploits. For certain components that are out of reach through experiments, we propose well-reasoned speculations about their inner working mechanisms. We have responsibly reported all security findings presented in this paper to the NVIDIA PSIRT Team.
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Grey Ballard · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2020
Abstract not provided.
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Michael Patterson · 2013
In the past decade Graphics Processing Units (GPUs) have advanced from simple fixedfunction graphics accelerators to fully-programmable multi-core architectures capable of supporting thousand of concurrent threads. Their use has spread from the specialized field of graphics into more general processing domains ranging from biomedical imaging to stock market prediction. Despite their increased computational power and range of applications, the security implications of GPUs have not been carefully studied. It has been assumed that the use of a GPU as a coprocessor with physically separate memory space, minimal support for multi-user programming, and limited I/O capability inherently guarantees security. This research challenges this assumption by demonstrating multiple security vulnerabilities in the current GPU computing infrastructure. Specifically, it focuses on the following three areas: 1. Denial-of-Service by overwhelming the capabilities of the GPU so it is unable to provide responsiveness to the host operating system. 2. Information leakage due to the way that modern GPUs fail to randomize pointers and zero out memory. 3. The use of GPUs to assist CPU-resident malware through obfuscation and unpacking or acceleration of computational intensive tasks such as password cracking or encryption. Through the use of WebGL and CUDA, we successfully developed a proof of concept attack for the first two vulnerabilities listed above. For the third, we considered several different types of attacks and their implications. In all cases we also suggest possible security measures to fix these vulnerabilities. While the impact of each of these particular exploits is currently hardware and OS specific, current trends in GPU architecture indicate that these problems are only going to rise in importance going forward.
Cited by 9Open access
Tyler Bransfield, Sanjeev Gunawardena · Proceedings of the Institute of Navigation ... International Technical Meeting/Proceedings of the ... International Technical Meeting of The Institute of Navigation · 2023
By storing correlation results in individual bins according to fractional chip phase and transition state, the average shape of a satnav signal’s spreading code chip transient response can be estimated. Current methods for software-based processing of chip shape results are computationally inefficient and make processing time prohibitive. This paper presents a GPU based method of generating chip shape results that achieves real time performance. Several GPU based methods are compared in addition to a multi-threaded CPU based method.
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Guillaume Colin de Verdière · 2009
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Zanden, TC van der, Bodlaender, HL Hans · TU/e Research Portal (Eindhoven University of Technology) · 2017
<p>We present a parallel algorithm for computing the treewidth of a graph on a GPU. We implement this algorithm in OpenCL, and experimentally evaluate its performance. Our algorithm is based on an O∗(2<sup>n</sup>)-time algorithm that explores the elimination orderings of the graph using a Held-Karp like dynamic programming approach. We use Bloom filters to detect duplicate solutions. GPU programming presents unique challenges and constraints, such as constraints on the use of memory and the need to limit branch divergence. We experiment with various optimizations to see if it is possible to work around these issues. We achieve a very large speed up (up to 77×) compared to running the same algorithm on the CPU.</p>
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