Antoine Kaufmann, Simon Peter, Naveen Kr. Sharma et al. · ACM SIGPLAN Notices · 2016
The recent surge of network I/O performance has put enormous pressure on memory and software I/O processing sub systems. We argue that the primary reason for high memory and processing overheads is the inefficient use of these resources by current commodity network interface cards (NICs). We propose FlexNIC, a flexible network DMA interface that can be used by operating systems and applications alike to reduce packet processing overheads. FlexNIC allows services to install packet processing rules into the NIC, which then executes simple operations on packets while exchanging them with host memory. Thus, our proposal moves some of the packet processing traditionally done in software to the NIC, where it can be done flexibly and at high speed. We quantify the potential benefits of FlexNIC by emulating the proposed FlexNIC functionality with existing hardware or in software. We show that significant gains in application performance are possible, in terms of both latency and throughput, for several widely used applications, including a key-value store, a stream processing system, and an intrusion detection system.
Cited by 11
Antoine Kaufmann, Simon Peter, Naveen Kr. Sharma et al. · ACM SIGARCH Computer Architecture News · 2016
The recent surge of network I/O performance has put enormous pressure on memory and software I/O processing sub systems. We argue that the primary reason for high memory and processing overheads is the inefficient use of these resources by current commodity network interface cards (NICs). We propose FlexNIC, a flexible network DMA interface that can be used by operating systems and applications alike to reduce packet processing overheads. FlexNIC allows services to install packet processing rules into the NIC, which then executes simple operations on packets while exchanging them with host memory. Thus, our proposal moves some of the packet processing traditionally done in software to the NIC, where it can be done flexibly and at high speed. We quantify the potential benefits of FlexNIC by emulating the proposed FlexNIC functionality with existing hardware or in software. We show that significant gains in application performance are possible, in terms of both latency and throughput, for several widely used applications, including a key-value store, a stream processing system, and an intrusion detection system.
Cited by 8
Zhuoer Shi, Zheng Bao, Licheng Jiao et al. · 2007
Arbitrary-shape wavelet packet transform (ASWPT) is presented as an adjustment of the traditional quad-tree wavelet packet transform. The group normalization (GN) and softer logic masking (SLM) techniques are introduced for image restoration with optimal visual result and high PSNR. I. INTRODUCTION As an important development of wavelet theory, wavelet packet transform (WPT) [8, 10, 12, 14, 16] overcomes the drawbacks that high-frequency analysis tend to be less refined when the scale increases. Traditional WPT limited to quad-tree decomposition that the cost function is calculated and compared between each parent node and her/his one "quad-offspring" (namely, LL, HL, LH and HH) to truncate the "branches" and obtain the optimal tree structure. However, the quad-tree basis set is not large enough to obtain the "best basis". Egger and Li [5] developed an extension structure of wavelet coefficients, but the structure is fixed without additional freedom. We construct arbitrary shape wave...
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Nikos Pleros, H. Avramopoulos · 2004
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W. Eatherton, Don Steiss, James Markevitch · 2008
This article consists of a collection of slides from the conference presentation. Some of the specific topics discussed include: an overview of Cisco's ASR-1000 Quantum Flow Processor; Architecture and Implementation Tradeoffs; Software Development and Debug Environments; Silicon Details and Design Methodology; and Results.
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Jiaxin Lei, Manish Munikar, Hui Lu et al. · 2023
Overlay networks serve as the de facto network virtualization technique for providing connectivity among distributed containers. Despite the flexibility in building customized private container networks, overlay networks incur significant performance loss compared to physical networks (i.e., the native). The culprit lies in the inclusion of multiple network processing stages in overlay networks, which prolongs the network processing path and overloads CPU cores. In this paper, we propose mFlow, a novel packet steering approach to parallelize the in-kernel data path of network flows. mFlow exploits packet-level parallelism in the kernel network stack by splitting the packets of the same flow into multiple micro-flows, which can be processed in parallel on multiple cores. mFlow devises new, generic mechanisms for flow splitting while preserving in-order packet delivery with little overhead. Our evaluation with both micro-benchmarks and real-world applications demonstrates the effectiveness of mFlow, with significantly improved performance – e.g., by 81% in TCP throughput and 139% in UDP compared to vanilla overlay networks. mFlow even achieved higher TCP throughput than the native (e.g., 29.8 vs. 26.6 Gbps).
Cited by 2
Hirokazu Takenouchi · IEICE Transactions on Electronics · 2005
Asynchronous optical packet switching (OPS) is a promising solution to support the continuous growth of transmission capacity demand. It has been, however, quite difficult to implement key functions needed at the node of such networks with all-optical approaches. We have proposed a new optoelectronic system composed of a packetby-packet optical clock-pulse generator (OCG), an all-optical serial-to-parallel converter (SPC), a photonic parallel-to-serial converter (PSC), and CMOS circuitry. The system makes it possible to carry out various required functions such as buffering (random access memory), optical packet compression/decompression, and optical label swapping for high-speed asynchronous optical packets.
Cited by 2
Yohei Kuga, Takeshi Matsuya, Hiroaki Hazeyama et al. · China Communications · 2014
We propose a new scripting model for rapid and easier development of packet processing using shell scripts. In this paper we present EtherPIPE, a character network I/O device, that allows the programmer to access network traffic data as a file through UNIX commands. By setting a UNIX pipe "|" from or to EtherPIPE's output or input with UNIX commands, packets can be easily processed, executing functions such as packet filtering, packet capturing, generating arbitrary packets, and rewriting header information. In order to prove the utilities of our model, we have developed FPGA-based EtherPIPE adapter using a commodity FPGA card and a character device driver featuring new offloading functions. With our prototype implementation, packet scripting works at 1Gbps wire-speed, receiving packets with precise hardware timestamps. This paper argues for use cases of the EtherPIPE, and discusses enhanced formats of character devices for easier network scripting.).
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Takashi Egawa, Koji Hino, Yohei Hasegawa · Lecture notes in computer science · 2001
Cited by 4Open access
Javier Verdú, Mario Nemirovsky, Mateo Valero · 2008
Mostly emerging network applications comprise deep packet inspection and/or stateful capabilities. Stateful workloads present limitations that reduce the exploitation of parallelism, unlike other network applications that show marginal dependencies among packets. In addition, differences among packet processing lead to significant negative interaction between threads, especially in the memory hierarchy.
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Technology Journal Network, An Ixp, Matthew Adiletta et al. · 2002
The IXP2800 is the high-end device of a family of network processors developed by Intel Corporation. It is designed for 10 Gigabit/sec data rates, with typical usage in packet forwarding systems. It can be configured with large amounts of dynamic and static storage for buffering hundreds of thousands of packets for up to a million Internet Transmission Control Protocol (TCP) connections. The programmability and parallel nature of this processor chip make it an ideal choice when high performance and ability to quickly adapt to new network standards are the requirements.
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H. Jonathan Chao, Masanori Bando · 2011
With the rapid growth of the user population and the traffic volume of the Internet in the past decade, the continuous improvement of network equipment becomes a solid necessity for today's and tomorrow's Internet. It is urgent to introduce enhanced architectures and algorithms to sustain future demands in terms of speed and scalability. In this thesis, we focus on two core network applications: (1) Internet Protocol (IP) route lookup and (2) Deep Packet Inspection (DPI) for Intrusion Detection and Prevention System (IDPS). We explore previous related work, define the problem, and state our motivation at the beginning of each chapter. We propose multiple novel algorithms, architectures, and data structures to improve throughput and scalability for these two applications. All proposed schemes are evaluated with software-based simulation and with hardware prototyping on Field Programmable Gate Arrays (FPGAs) and Dynamic Random Access Memory (DRAM) technology.
To anticipate market demands, our target throughput for both applications is 100-Gbps and beyond. For a 100-Gbps link, 250 million packets for IP route lookup for the minimum packet length and 12.5 billion characters need to be processed in 1 second. In other words, there is only 4nsec to perform IP route lookup and 80psec to complete one character inspection in DPI. It has been a challenge to achieve this performance while maintaining excellent scalability and updatability. In this thesis, we propose solutions to overcome these challenges. In particular, we introduce a greater than 100-Gbps IP route look-up scheme with one FPGA and four DRAM chips, and 100-Gbps DPI with Regular Expression capability using pre-filtering technology.
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Frederick W. Vook · OhioLink ETD Center (Ohio Library and Information Network) · 1992
Cited by 1Open access
Fong Pong, Nian-Feng Tzeng · 2008
This work deals with an architectural framework to enable application-layer packet processing for lowered processing latency and enhanced throughput. Creating an "Ethereal memory" shared by application programs and network interface drivers, the proposed framework realizes application-layer packet processing through Ethereal memory (APPEAL). Unlike earlier solutions based on network processors or field programmable gate arrays, APPEAL supports packet processing software execution in regular OS environments (like Linux) on general-purpose multi-core processors (like Intelreg Core 2 Extreme and Broadcom BCM1480 SoC products). It facilitates fast packet processing code development and lets applications have direct accesses to data contained in Ethereal memory, totally eliminating the need of packet copies between user space and kernel space and of system calls. Without kernel overhead during application layer packet processing, APPEAL is shown by our empirical results obtained from a hardware platform comprising three BCM 1480 SoC's, to enjoy far smaller latency (dropped by as much as 58%) and to more than double throughput, when carrying out network address and port translation.
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Cristian Soviani, Ilija Hadžić, Stephen A. Edwards · Proceedings - ACM IEEE Design Automation Conference · 2006
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations.
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Michael Attig, Gordon Brebner · 2006
This paper considers the elaboration of custom pipelines for network packet processing, built upon flexible programmability of pipeline stage granularity. A systematic procedure for accurately characterizing throughput, latency, and FPGA resource requirements, of different programmed pipeline variants is presented. This procedure may be exploited at design time, configuration time, or run time, to program pipeline architectures to meet specific networking application requirements. The procedure is illustrated using three case studies drawn from real-life packet processing at different levels of networking protocol. Detailed results are presented, demonstrating that the procedure estimates pipeline characteristics well, thus allowing rapid architecture space exploration prior to elaboration
Cited by 4
Stephen A. Edwards · Columbia Academic Commons (Columbia University) · 2007
Packet processing is an essential function of state-of-the-art network routers and switches. Implementing packet processors in pipelined architectures is a well-known, established technique, albeit different approaches have been proposed. The design of packet processing pipelines is a delicate trade-off between the desire for abstract specifications, short development time, and design maintainability on one hand and very aggressive performance requirements on the other. This thesis proposes a coherent design flow for packet processing pipelines. Like the design process itself, I start by introducing a novel domain-specific language that provides a high-level specification of the pipeline. Next, I address synthesizing this model and calculating its worst-case throughput. Finally, I address some specific circuit optimization issues. I claim, based on experimental results, that my proposed technique can dramatically improve the design process of these pipelines, while the resulting performance matches the expectations of hand-crafted design. The considered pipelines exhibit a pseudo-linear topology, which can be too restrictive in the general case. However, especially due to its high performance, such an architecture may be suitable for applications outside packet processing, in which case some of my proposed techniques could be easily adapted. Since I ran my experiments on FPGAs, this work has an inherent bias towards that technology; however, most results are technology-independent.
Cited by 2Open access
Harald Widiger, Stephan Kubisch, Dirk Timmermann · 2007
In modern network applications and especially in Access Networks, the demands towards functionality and throughput are rising permanently. Furthermore, telecommunication carriers have different and changing requirements towards Access Network equipment. They are thus demanding a great deal of flexibility in IP-DSLAMS. To satisfy these various needs, highly flexible and particularly high performing packet processors are required. We propose an architecture for hardware modules, which joins the advantages of software and hardware solutions targeting packet processing. Our architecture provides a powerful and fast solution due to hardware implementation. Furthermore, it enables flexible and adaptive packet processors for different needs and configurations comparable to a software solution based on a network processor. This is accomplished without any overhead of unnecessary functionality and without the difficulties, which occur when it comes to adjusting pure ASIC packet processors to different tasks. Our architectural approach thus provides a good solution for packet processing.
Cited by 2
Hoang V. Nguyen · OhioLink ETD Center (Ohio Library and Information Network) · 2016
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Kohout, Pavel · Brno University of Technology Digital Library (Brno University of Technology) · 2019
S rostoucími rychlostmi a komplexností počítačových sítí vznikají požadavky na vytváření výkonných zařízení, která jsou schopna provádět sběr statistik a měnit svoji funkcionalitu podle požadavků síťových administrátorů. Tyto požadavky mohou být popsány pomocí specializovaných programovacích jazyků, například jazykem P4. V rámci této bakalářské práce byl proveden návrh, implementace, testování a integrace modulů stavových pamětí registrů a čítačů do systému překladače jazyka P4 do technologie FPGA. Vytvořený systém podporuje sběr statistik popsaných v jazyce P4 na rychlosti až 100 Gb/s.
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