Quintero Gómez, Juan David · Institutional Repository University of Antioquia (University of Antioquia) · 2020
ABSTRACT : Due to the advances of the so-called Next Generation Sequencing technologies (NGS), the amount of genetic information has been significantly increased and it is expected to continue growing, so there is a need to efficiently storing this type of information and an alternative to solve it, is the compression. In many phases of this process, suffix array is a fundamental part and their construction needs a lot of time. In this degree thesis, an algorithm was designed for the construction of suffix arrays on DNA sequences that combine different techniques and levels of parallelization and contribute to improving the performance in the compression process of this type of data.
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D. D. Coon, A. G. U. Perera · International Journal of Infrared and Millimeter Waves · 1987
Cited by 4
A. Cowley, R.C. Patterson · Electronics Letters · 1971
Fabrication of parallel arrays of silicon IMPATT diodes in which the arrays are formed in a single diode chip is described. The technique includes formation of an integral heatsink for the diode arrays during wafer processing. For a given total active device area, the use of a parallel array of smaller diodes, rather than one large diode, allows a significant reduction in thermal impedance and consequently larger power-dissipation capability. The contribution shown in the letter is the ease and economy with which parallel arrays on an integral heatsink can be fabricated and handled as a single entity. In a diode operated at 6.4 GHz, 3.5 W of c.w. output power has been achieved with a room-temperature copper heatsink and a junction temperature of about 280°C.
Cited by 6
A L Stewart · Journal of Parallel and Distributed Computing · 1995
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Xiaoli Zhao, He yun-hong, Jiu‐sheng Li · 2010
This letter proposed a novel series-parallel microstrip array antenna. The presented antenna is fabricated and measured. The frequency band of the designed antenna is from 2.351 to 2.540 GHz, realized in a commercial Teflon printed-circuit board with a permittivity of 2.65 and thickness of 1 mm. The average gain of E-plane of the proposed antenna is about 17.175 dBi in the working frequency band. The antenna size is 291 × 291 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured results show that the proposed antenna is applied for WLAN application.
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H. Wang, F.H. Groen, S. F. Pereira et al. · Research Repository (Delft University of Technology) · 2004
We present an analysis of the reading capability of a novel optical pickup consisting of a single-mode and a multi-mode rectangular waveguide. According to the simulations, if one has prior information about the structure of the disk, superresolution readout could be achieved. The proposed system has the advantage to be compact and should be straightforward to be extended to arrays. The working distance of this optical pickup can be adapted from near- to farfield by changing the length of the multi-mode waveguide.
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Chau-Jy Lin · International Journal of Computer Mathematics · 1991
Given n items, a parallel algorithm for generating all the n! permutations is presented. The computational model used is a linear array which consists of n identical processing elements with a simple structure. One permutation is produced at each other time step. The elapsed time to produce a permutation is independent of the integer n. The basic idea used is the iterative method and the exchange of two consecutive components in an existing permutation. The design procedures of this algorithm are considered in detail. The ranking and unranking functions of the required permutations are also discussed.
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P. Helen Ch, K. G. Subramanian, C. Martin-vide et al. · 2008
A simple and effective syntactic method of description of picture patterns of rectangular arrays of symbols is proposed. The method is based on contextual grammars of Marcus(1969) guided by trajectories in the generation process.The resulting grammar is called Parallel contextual array grammar with contexts shuffled on trajectories. This grammar is capable of describing pictorial patterns that cannot be handled by certain other contextual array grammars introduced in the literature. 1.
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Zhipeng Cao, Xinqiang Yan, William A. Grissom · Magnetic Resonance in Medicine · 2015
Array-compressed pulse design jointly identifies the transmit coil array compression weights and RF pulses that perform best for a specific parallel excitation application. Magn Reson Med 76:1158-1169, 2016. © 2015 Wiley Periodicals, Inc.
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Jean-François Collard⋆ · Lecture notes in computer science · 1999
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P. Helén Chandra, Carlos Martı́n-Vide, K. G. Subramanian et al. · WORLD SCIENTIFIC eBooks · 2005
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Jun Tanida, Yoshiki Ichioka · 1985
A novel optical digital computing system called Optical Parallel Array Logic System (OPALS) is presented, which can execute cellular logic 1 in parallel. The system is constructed on the basis of the concept of optical array logic. The pure optical version of the OPALS can be realized by using a dynamic optical coding technique and optical correlation by a multi-focus imaging system. Although the OPALS is still a conceptual system, it would be expected to be a prototype of optical digital computing systems in future.
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Shukhrov, Yury · Aaltodoc (Aalto University) · 2019
The suffix array is an array of sorted suffixes in lexicographic order, where each sorted suffix is represented by its starting position in the input string. It is a fundamental data structure that finds various applications in areas such as string processing, text indexing, data compression, computational biology, and many more. Over the last three decades, researchers have proposed a broad spectrum of suffix array construction algorithms (SACAs). However, the majority of SACAs were implemented using sequential and parallel programming models. The maturity of GPU programming opened doors to the development of massively parallel GPU SACAs that outperform the fastest versions of suffix sorting algorithms optimized for the CPU parallel computing. Over the last five years, several GPU SACA approaches were proposed and implemented. They prioritized the running time over lightweight design. In this thesis, we design and implement a lightweight massively parallel SACA on the GPU using the prefix-doubling technique. Our prefix-doubling implementation is memory-efficient and can successfully construct the suffix array for input strings as large as 640 megabytes (MB) on Tesla P100 GPU. On large datasets, our implementation achieves a speedup of 7-16x over the fastest, highly optimized, OpenMP-accelerated suffix array constructor, libdivsufsort, that leverages the CPU shared memory parallelism. The performance of our algorithm relies on several high-performance parallel primitives such as radix sort, conditional filtering, inclusive prefix sum, random memory scattering, and segmented sort. We evaluate the performance of our implementation over a variety of real-world datasets with respect to its runtime, throughput, memory usage, and scalability. We compare our results against libdivsufsort that we run on a Haswell compute node equipped with 24 cores. Our GPU SACA is simple and compact, consisting of less than 300 lines of readable and effective source code. Additionally, we design and implement a fast and lightweight algorithm for checking the correctness of the suffix array.
Cited by 1Open access
Clemens Grelck, Cédric Blom · International Journal of Parallel Programming · 2020
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Gaétan Hains, John Mullins · 1996
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Ronald Harry Klausewitz · 1998
The processing of large arrays on parallel systems has many applications. One of these is the solution of partial differential equations using the iterative calculation approach. This method is very computationally intensive, and, depending on the method of partitioning and computation can be very communication intensive. The last definitive work on this subject was done in 1991. The methods now commonly used need to be re-examined to see if there is a method of segmentation, computation and communication that can speed up such a solution on emerging popular MIMD and clustered systems by a significant factor. If so that method could be a large contribution to the present and future use of computers in these problems.
In array segmentation the problem of data communications arises at the boundaries of the segments. Values that must be used in calculation are in different machines and must be accessed to complete the calculations. The conventional approach is to exchange boundary values whenever they are needed, resulting in a high volume of short-length communications. The alternative, developed here, is to do all of the calculations in one segment until no further calculations are possible, then exchange a large piece of the original segment. This has the effect of decreasing the communications volume and increasing the average message length. In parallel machines with slow communications set-up, that results in a solution speed up of better than 3 to 1 and could result in a better than 5 to 1 speedup on clustered systems.
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Yoshiki Ichioka · 1994
Introduction We consider an optical computing architecture called pure optical parallel array logic system (P-OPALS), for which we propose logical foundation of the P-OPALS called single-input optical array logic (S-OAL) . On the P-OPALS, high density images can be processed in parallel using the optical system with high resolving power. Based on the proposed architecture, an experimental system of the P-OPALS is constructed by using three optical techniques: birefringent encoding, selectable discrete correlator, and birefringent decoding. To show processing capability of the P-OPALS, some basic parallel operations are attempted. The results obtained indicate that image consisting of 300\\Theta100 pixels can be processed in parallel on the experimental P-OPALS. 2. P-OPALS The OPALS is an optical digital computing system for 2-D information processing which consists of encoder, correlator, decoder, and feedback-paths. The P-OPALS is a pure optical version of OPALS, in which
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Purdue E-pubs, Ko-yang Wang, Ko-yang Wang et al. · 1990
In this paper, we discuss a program transformation technique called array reshaping. Array reshaping is an aggressive program transformation technique that modifies the shape of the array storage at compile-time for efficient execution on parallel architectures. It can be used to minimize the local storage for local copies of data or change the patterns that arrays are stored and referenced. For shared-memory architectures, it can be used to copy subsets of arrays to local memories in blocks to speed up the data references. For distributed-memory architectures, this technique can be used to minimize conununication between processors and optimize the data storage. Array reshaping also eliminates some of the needs to hand optim-ize the storage space and thus allows the user to specify algorithms in a more intuitive way. Array reshaping functions and some examples and heuristics for utilizing the array reshaping are discussed.
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David Evans, Ossama K. Muslih · International Journal of Computer Mathematics · 2001
In this paper the Instruction Systolic Array (ISA) is implemented using a soft systolic simulation system and a comparison given for the programming and simulation of a parallel merging program with the Processor Array (PA) and Instruction Broadcast Array (IBA). Finally the relationships between the ISA, IBA and PA VLSI computing structures are given.
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Koji Mori, S. Yamaguchi, A. Higasiura et al. · 2002
There has been an increasing demand for downsizing and upgrading electrical and electronic appliances ranging from consumer products to service machinery. As one approach to materialization, inverter-controllers and switching power supplies are advancing toward higher-frequency operation. In regard to coil wire intended to reduce the HF resistance induced by the skin effect, those units have applied Litz wire comprised of stranded enamelled wires or tape-insulated copper foil or copper sheet. The Litz wire has weak points of workability for winding and a low-space factor. Likewise, copper foil or copper sheet produces considerable heat due to eddy current loss and also difficulty in its edge insulation treatment. The authors have developed a high-frequency-compatible wire which makes use of a remarkable combination of Litz wire and copper foil or sheet. Upon close analysis, a parallel array wire strip comprised of multiple wires arranged in tape form has been developed. This paper discusses the general characteristics and some sample applications.
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