This report will cover the design of an array of 8×8 lb processors implemented in 3μ-m NMOS technology with 81,000 transistors, providing two dimensional data processing.

Cited by 19

Array processor support in GIPSY

Gregg Roland Fabregas · VTechWorks (Virginia Tech) · 1989

The CSPI mini-MAP array processor is supported for use with a RATFOR preprocessor in the software environment defined by the Generalized Image Processing System (GIPSY). A set of interface routines presents the mini-MAP as a tightly-coupled slave processor with well-defined rules for control from the host computer. The slave is programmed by adapting host-based software, using a proscribed set of guidelines for conversion. A software protocol has been defined to allow mini-MAP data memory to be allocated dynamically. Several examples of modified GIPSY commands are examined.

Cited by 0Open access

Array processor with multiple broadcasting

V. Krishna Kumar, C.S. Raghavendra · ACM SIGARCH Computer Architecture News · 1985

article Free Access Share on Array processor with multiple broadcasting Authors: V. K. Prasanna Kumar Department of Electrical Englneerlng-Systems, University of Southern California, Los Angeles, CA Department of Electrical Englneerlng-Systems, University of Southern California, Los Angeles, CAView Profile , C. S. Raghavendra Department of Electrical Englneerlng-Systems, University of Southern California, Los Angeles, CA Department of Electrical Englneerlng-Systems, University of Southern California, Los Angeles, CAView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 2–10https://doi.org/10.1145/327070.327110Published:01 June 1985Publication History 27citation230DownloadsMetricsTotal Citations27Total Downloads230Last 12 Months14Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Cited by 36

DAP—a distributed array processor

S.F. Reddaway · ACM SIGARCH Computer Architecture News · 1973

An array of very simple processing elements is described each with a local semiconductor store. The array may also be used as main storage. Bit-organisation gives great flexibility, including the minimisation of word length. Use of MSI and LSI is helped by the simplicity of the serial design. Using 15-bit fixed point, the theoretical performance of a 72 × 128 array is about 10 8 multiplications or 10 9 additions per second. Comparisons are made with other architectures. Meteorology is considered as an application. It is attractive to have the whole problem in the array storage.

Cited by 128Open access

ANDROX Parallel Image Array Processor

Phil Dunbar · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1988

A single board parallel processor designed for operations on images is described. The system is based on the Multiple Instruction, Multiple Data (MIMD) model with four independent signal processing nodes and a large global image memory. Image acquisition is provided for four simultaneous video inputs, and video output for color or monochrome display. Examples of the system's application for two dimensional FFTs, color transformations, and texture modeling are given.

Cited by 0

Array processor architecture connection network

Shafer, Philip E., Barnes, George H., Lundstrom, Stephen F. · NASA Technical Reports Server (NASA)

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

Cited by 0Open access

Pseudo MIMD array processor—AAP2

Toshiyuki Kondo, Toshio Tsuchiya, Toshihiro Kitamura et al. · ACM SIGARCH Computer Architecture News · 1986

A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications. A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications.

Cited by 17

DAP---a distributed array processor

S. F. Reddaway · 1973

An array of very simple processing elements is described each with a local semiconductor store. The array may also be used as main storage.

Cited by 89

Dependable Reconfigurable Processor Array (RPA)

HEBERT, Nicolas, TORRES, Lionel · 2011

Cette thèse s'inscrit dans un contexte où chaque saut technologique, voit apparaitre des circuits intégrés produits de plus en plus tôt dans la phase de qualification et où la technologie de ces circuits intégrés se rapproche de plus en plus des limitations physiques de la matière. Malgré des contre-mesures technologiques, on se retrouve devant un taux de défaillance grandissant ce qui crée des conditions favorables au retour des techniques de tolérance aux fautes sur les circuits intégrés non critiques.La densité d'intégration atteinte aujourd'hui nous permet de considérer les réseaux reconfigurables de processeur comme des architectures SoC d'avenir. En effet, l'homogénéité de ces architectures laisse entrevoir des reconfigurations possibles de la plateforme qui permettraient d'assurer une qualité de service et donc une fiabilité minimum en présence de défauts. Ainsi, de nouvelles solutions de protection doivent être proposées pour garantir le bon fonctionnement des circuits non plus uniquement au niveau de quelques sous-fonctionnalités critiques mais au niveau architecture système lui-même.En s'appuyant sur ces prérogatives, nous présentons une méthode de protection distribuée et dynamique innovatrice, D-Scale. La méthode consiste à détecter, isoler et recouvrir les systèmes en présence d'erreurs de type crash . La détection des erreurs qui ont pour conséquence un crash de la plateforme est basée sur un mécanisme de messages de diagnostique échangés entre les unités de traitement. La phase de recouvrement est quant à elle basée sur un mécanisme permettant la reconfiguration de la plateforme de manière autonome. Une implémentation de cette protection matérielle et logicielle est proposée. Le coût de protection est réduit afin d'être intégré dans de futures architectures multiprocesseurs. Finalement, un outil d'évaluation d'impacte des fautes sur la plateforme est aussi étudié afin de valider l'efficacité de la protection.

Cited by 0Open access

Design of array processor systems

Peisu Xia, Xinwo Fang, Yuxiang Wang et al. · Journal of Computer Science and Technology · 1987

Cited by 0

The Distributed Array Processor (DAP)

D. Parkinson · Computer Physics Communications · 1983

Cited by 49

A GENERALIZED MAPPING OF 2-D ARRAY PROCESSOR TO LINEAR ARRAY PROCESSOR AND ITS APPLICATIONS

Kuo‐Liang Chung, Richard Chia-Tung Lee, Yu‐Chih Lin · Parallel algorithms and applications · 1995

In a previous paper [14], Yang and Lee showed a mapping method which maps a 2-dimensional single-wavefront array processor to a linear array processor if there is only one wavefront propagating and never backtracks. In this paper, we shall discuss a more general case where the wavefront activates only a limited part of each diagonal. The mapping method which is more general than that given by Yang and Lee is presented here. We then show how this mapping can be applied to synthesize the stereo-matching algorithm on a linear array processor, where the number of processors depends upon the bandwidth of the wavefront.

Cited by 1

Semantic Network Array Processor as a

Massively Parallel Computing, Hiroaki Kitano · 1992

This paper demonstrates the utility of the Semantic Network Array Processor (SNAP) as a massively parallel platform for high performance and large-scale natural language processing systems. SNAP is an experimental massively parallel machine which is dedicated to, but not limited to, the natural language processing using semantic networks. In designing the SNAP, we have investigated various natural language processing systems and theories to determine the scope of the hardware support and a set of micro-coded instructions to be provided. As a resuit, SNAP employs an extended markerpassing model and a dynanically modifiable network model. A set of primitive instructions is micro-coded to directly support a parallel marker-passing, bitoperations, nunreric operations, network modifications, and other essential functions for natural language processing. This paper demonstrates the utility of SNAP for various paradigms of natural language processing. We have discovered that the SNAP provides milliseconds or microseconds performance on several important ap phcations such as the memory-bmqed parsing and translation, classification-based parsing, and VLKB search. Also, we argue that there are numerous opportunities in the NLP community to take advantages of the computational power of tile SNAP.

Cited by 0

Transputer array processor for physiological modelling

N.D. Black, K. Adamson, G. Donnan · Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society · 1992

A concurrent model of the basilar membrane (BM) using the Occam programming language is presented. The BM is represented by the concatenation of independent electrical sections, each simulating the physiological activity of different elemental sections of the membrane. The structure of the concurrent model is largely derived from the electrical indicating potential design benefits for more complex models.

Cited by 0

A Systematically Designed Binary Array Processor

Reeves · IEEE Transactions on Computers · 1980

A class of binary array processors (BAP) have evolved over the past 20 years primarily intended for image-processing applications. The advent of large-scale integrated-circuit technology makes the construction of these processors feasible. In this paper three basic instruction types that characterize a BAP are defined and the systematic design of a processor called BASE is described in detail. Two forms of BASE are discussed, a fully parallel version and an add-on unit for a conventional computer. The systematic design has enabled an assembly language with a simple, APL-like syntax to be developed. Several program examples to illustrate features of the processor are given.

Cited by 43